Add more debugging information to tests

Author: fineg74

SYCL/ESIMD/lsc/lsc_predicate.cpp

@@ -14,8 +14,6 @@
 
 #include "../esimd_test_utils.hpp"
 
-#include <algorithm>
-#include <cmath>
 #include <numeric>
 #include <sycl/ext/intel/esimd.hpp>
 #include <sycl/sycl.hpp>
@@ -77,7 +75,7 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
                                            pred_disable);
           });
     });
-    q.wait();
+    q.wait_and_throw();
     buf_0.template get_access<access::mode::read_write>();
     buf_1.template get_access<access::mode::read_write>();
     buf_2.template get_access<access::mode::read_write>();
@@ -159,7 +157,7 @@ template <unsigned SIMDSize> int testUSM(queue q) {
                                            pred_disable);
           });
     });
-    q.wait();
+    q.wait_and_throw();
   } catch (sycl::exception e) {
     std::cout << "SYCL exception caught: " << e.what();
     sycl::free(vec_0, q);

SYCL/ESIMD/lsc/lsc_predicate_stateless.cpp

@@ -16,8 +16,6 @@
 
 #include "../esimd_test_utils.hpp"
 
-#include <algorithm>
-#include <cmath>
 #include <numeric>
 #include <sycl/ext/intel/esimd.hpp>
 #include <sycl/sycl.hpp>
@@ -79,7 +77,7 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
                                            pred_disable);
           });
     });
-    q.wait();
+    q.wait_and_throw();
     buf_0.template get_access<access::mode::read_write>();
     buf_1.template get_access<access::mode::read_write>();
     buf_2.template get_access<access::mode::read_write>();
@@ -91,10 +89,28 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
 
   auto error = 0;
   for (auto i = 0; i != size; ++i) {
-    error += vec_0[i] != 2 * i;
-    error += vec_1[i] > 0;
-    error += vec_2[i] != i;
-    error += vec_3[i] != i;
+    if (vec_0[i] != 2 * i) {
+      ++error;
+      std::cout << " Accessor Test 1 out[" << i << "] = 0x" << std::hex
+                << vec_0[i] << " vs etalon = 0x" << 2 * i << std::dec
+                << std::endl;
+    }
+    if (vec_1[i] > 0) {
+      ++error;
+      std::cout << " Accessor Test 2 out[" << i << "] = 0x" << std::hex
+                << vec_1[i] << " vs etalon = 0x" << 0 << std::dec << std::endl;
+    }
+    if (vec_2[i] != i) {
+      ++error;
+      std::cout << " Accessor Test 3 out[" << i << "] = 0x" << std::hex
+                << vec_2[i] << " vs etalon = 0x" << i << std::dec << std::endl;
+    }
+
+    if (vec_3[i] != i) {
+      ++error;
+      std::cout << " Accessor Test 4 out[" << i << "] = 0x" << std::hex
+                << vec_3[i] << " vs etalon = 0x" << i << std::dec << std::endl;
+    }
   }
   std::cout << "Accessor lsc predicate test ";
   std::cout << (error != 0 ? "FAILED" : "passed") << std::endl;