[SYCL] Rename ROCm to HIP in on-devce tests

npmiller · npmiller · commit d05cf86482fc · 2021-09-13T15:39:45.000+01:00
diff --git a/SYCL/AtomicRef/atomic_memory_order.cpp b/SYCL/AtomicRef/atomic_memory_order.cpp
@@ -3,7 +3,7 @@
 // RUN: %CPU_RUN_PLACEHOLDER %t.out
 // RUN: %GPU_RUN_PLACEHOLDER %t.out
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
-// L0, OpenCL, and ROCm backends don't currently support
+// L0, OpenCL, and HIP backends don't currently support
 // info::device::atomic_memory_order_capabilities
 // UNSUPPORTED: level_zero || opencl || hip
 
diff --git a/SYCL/AtomicRef/atomic_memory_order_acq_rel.cpp b/SYCL/AtomicRef/atomic_memory_order_acq_rel.cpp
@@ -3,9 +3,9 @@
 // RUN: %CPU_RUN_PLACEHOLDER %t.out
 // RUN: %GPU_RUN_PLACEHOLDER %t.out
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
-// L0, OpenCL, and ROCm backends don't currently support
+// L0, OpenCL, and HIP backends don't currently support
 // info::device::atomic_memory_order_capabilities
-// UNSUPPORTED: level_zero || opencl || rocm
+// UNSUPPORTED: level_zero || opencl || hip
 
 // NOTE: Tests load and store for acquire-release memory ordering.
 
diff --git a/SYCL/AtomicRef/atomic_memory_order_acq_rel_atomic64.cpp b/SYCL/AtomicRef/atomic_memory_order_acq_rel_atomic64.cpp
@@ -3,9 +3,9 @@
 // RUN: %CPU_RUN_PLACEHOLDER %t.out
 // RUN: %GPU_RUN_PLACEHOLDER %t.out
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
-// L0, OpenCL, and ROCm backends don't currently support
+// L0, OpenCL, and HIP backends don't currently support
 // info::device::atomic_memory_order_capabilities
-// UNSUPPORTED: level_zero || opencl || rocm
+// UNSUPPORTED: level_zero || opencl || hip
 
 // NOTE: Tests load and store for acquire-release memory ordering with 64-bit
 //       values.
diff --git a/SYCL/AtomicRef/atomic_memory_order_seq_cst.cpp b/SYCL/AtomicRef/atomic_memory_order_seq_cst.cpp
@@ -3,9 +3,9 @@
 // RUN: %CPU_RUN_PLACEHOLDER %t.out
 // RUN: %GPU_RUN_PLACEHOLDER %t.out
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
-// L0, OpenCL, and ROCm backends don't currently support
+// L0, OpenCL, and HIP backends don't currently support
 // info::device::atomic_memory_order_capabilities
-// UNSUPPORTED: level_zero || opencl || rocm
+// UNSUPPORTED: level_zero || opencl || hip
 
 // NOTE: Tests load and store for sequentially consistent memory ordering.
 
diff --git a/SYCL/AtomicRef/atomic_memory_order_seq_cst_atomic64.cpp b/SYCL/AtomicRef/atomic_memory_order_seq_cst_atomic64.cpp
@@ -3,9 +3,9 @@
 // RUN: %CPU_RUN_PLACEHOLDER %t.out
 // RUN: %GPU_RUN_PLACEHOLDER %t.out
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
-// L0, OpenCL, and ROCm backends don't currently support
+// L0, OpenCL, and HIP backends don't currently support
 // info::device::atomic_memory_order_capabilities
-// UNSUPPORTED: level_zero || opencl || rocm
+// UNSUPPORTED: level_zero || opencl || hip
 
 // NOTE: Tests load and store for sequentially consistent memory ordering with
 //       64-bit values.
diff --git a/SYCL/Basic/aspects.cpp b/SYCL/Basic/aspects.cpp
@@ -1,9 +1,8 @@
 // RUN: %clangxx -fsycl %s -o %t.out
 // RUN: env SYCL_DEVICE_FILTER=%sycl_be %t.out
 //
-// Hip is missing some of the parameters tested here so it fails with ROCm for
-// NVIDIA
-// XFAIL: rocm_nvidia
+// Hip is missing some of the parameters tested here so it fails with NVIDIA
+// XFAIL: hip_nvidia
 
 //==--------------- aspects.cpp - SYCL device test ------------------------==//
 //
diff --git a/SYCL/Basic/image/srgba-read.cpp b/SYCL/Basic/image/srgba-read.cpp
@@ -4,8 +4,7 @@
 
 // XFAIL: level_zero
 // UNSUPPORTED: cuda
-// UNSUPPORTED: rocm_nvidia
-// UNSUPPORTED: rocm_amd
+// UNSUPPORTED: hip
 
 #include <sycl/sycl.hpp>
 
diff --git a/SYCL/Basic/intel-ext-device.cpp b/SYCL/Basic/intel-ext-device.cpp
@@ -4,8 +4,7 @@
 //
 // REQUIRES: gpu
 // UNSUPPORTED: cuda
-// UNSUPPORTED: rocm_nvidia
-// UNSUPPORTED: rocm_amd
+// UNSUPPORTED: hip
 
 //==--------- intel-ext-device.cpp - SYCL device test ------------==//
 //
diff --git a/SYCL/Basic/span.cpp b/SYCL/Basic/span.cpp
@@ -3,8 +3,8 @@
 // RUN: %GPU_RUN_PLACEHOLDER %t.out
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
 //
-// Fails to release USM pointer on ROCm for NVIDIA
-// XFAIL: rocm_nvidia
+// Fails to release USM pointer on HIP for NVIDIA
+// XFAIL: hip_nvidia
 
 #include <numeric>
 #include <sycl/sycl.hpp>
diff --git a/SYCL/GroupAlgorithm/SYCL2020/all_of.cpp b/SYCL/GroupAlgorithm/SYCL2020/all_of.cpp
@@ -4,7 +4,7 @@
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
 //
 // Missing __spirv_GroupAll on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 
 #include "support.h"
 #include <CL/sycl.hpp>
diff --git a/SYCL/GroupAlgorithm/SYCL2020/any_of.cpp b/SYCL/GroupAlgorithm/SYCL2020/any_of.cpp
@@ -4,7 +4,7 @@
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
 //
 // Missing __spirv_GroupAny on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 
 #include "support.h"
 #include <CL/sycl.hpp>
diff --git a/SYCL/GroupAlgorithm/SYCL2020/exclusive_scan.cpp b/SYCL/GroupAlgorithm/SYCL2020/exclusive_scan.cpp
@@ -5,7 +5,7 @@
 //
 // Missing __spirv_GroupIAdd, __spirv_GroupBroadcast, __spirv_GroupSMin and
 // __spirv_GroupSMax on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 
 // TODO: enable compile+runtime checks for operations defined in SPIR-V 1.3.
 // That requires either adding a switch to clang (-spirv-max-version=1.3) or
diff --git a/SYCL/GroupAlgorithm/SYCL2020/group_broadcast.cpp b/SYCL/GroupAlgorithm/SYCL2020/group_broadcast.cpp
@@ -4,7 +4,7 @@
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
 //
 // Missing __spirv_GroupBroadcast on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 
 #include "support.h"
 #include <CL/sycl.hpp>
diff --git a/SYCL/GroupAlgorithm/SYCL2020/inclusive_scan.cpp b/SYCL/GroupAlgorithm/SYCL2020/inclusive_scan.cpp
@@ -5,7 +5,7 @@
 //
 // Missing __spirv_GroupIAdd, __spirv_GroupBroadcast, __spirv_GroupSMin and
 // __spirv_GroupSMax on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 
 // TODO: enable compile+runtime checks for operations defined in SPIR-V 1.3.
 // That requires either adding a switch to clang (-spirv-max-version=1.3) or
diff --git a/SYCL/GroupAlgorithm/SYCL2020/none_of.cpp b/SYCL/GroupAlgorithm/SYCL2020/none_of.cpp
@@ -4,7 +4,7 @@
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
 //
 // Missing __spirv_GroupAll and __spirv_GroupAny on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 
 #include "support.h"
 #include <CL/sycl.hpp>
diff --git a/SYCL/GroupAlgorithm/SYCL2020/permute_select.cpp b/SYCL/GroupAlgorithm/SYCL2020/permute_select.cpp
@@ -5,7 +5,7 @@
 //
 // Missing __spirv_SubgroupId, __spirv_SubgroupMaxSize, __spirv_SubgroupShuffle*
 // on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 //
 //==------------ permute_select.cpp -*- C++ -*-----------------------------===//
 //
diff --git a/SYCL/GroupAlgorithm/SYCL2020/reduce.cpp b/SYCL/GroupAlgorithm/SYCL2020/reduce.cpp
@@ -4,7 +4,7 @@
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
 //
 // Missinsg __spirv_GroupIAdd, __spirv_GroupSMin and __spirv_GroupSMax on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 
 // TODO: enable compile+runtime checks for operations defined in SPIR-V 1.3.
 // That requires either adding a switch to clang (-spirv-max-version=1.3) or
diff --git a/SYCL/GroupAlgorithm/SYCL2020/shift_left_right.cpp b/SYCL/GroupAlgorithm/SYCL2020/shift_left_right.cpp
@@ -5,7 +5,7 @@
 //
 // Missing __spirv_SubgroupId, __spirv_SubgroupMaxSize, __spirv_SubgroupShuffle*
 // on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 //
 //==------------ shift_left_right.cpp -*- C++ -*----------------------------==//
 //
diff --git a/SYCL/GroupAlgorithm/back_to_back_collectives.cpp b/SYCL/GroupAlgorithm/back_to_back_collectives.cpp
@@ -5,7 +5,7 @@
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
 //
 // Missing __spirv_GroupIAdd on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 
 #include <CL/sycl.hpp>
 #include <numeric>
diff --git a/SYCL/SpecConstants/2020/host_apis.cpp b/SYCL/SpecConstants/2020/host_apis.cpp
@@ -2,8 +2,7 @@
 // RUN: %t.out
 
 // UNSUPPORTED: cuda
-// UNSUPPORTED: rocm_nvidia
-// UNSUPPORTED: rocm_amd
+// UNSUPPORTED: hip
 
 #include <sycl/sycl.hpp>
 
diff --git a/SYCL/SpecConstants/2020/kernel_lambda_with_kernel_handler_arg.cpp b/SYCL/SpecConstants/2020/kernel_lambda_with_kernel_handler_arg.cpp
@@ -2,7 +2,7 @@
 // RUN: %CPU_RUN_PLACEHOLDER %t.out
 //
 // Hits an assert in the Lower Work Group Scope Code pass on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 
 // This test checks all possible scenarios of running single_task, parallel_for
 // and parallel_for_work_group to verify that this code compiles and runs
diff --git a/SYCL/SpecConstants/2020/non_native/aot_w_kernel_handler_wo_spec_consts.cpp b/SYCL/SpecConstants/2020/non_native/aot_w_kernel_handler_wo_spec_consts.cpp
@@ -2,7 +2,7 @@
 // RUN: %CPU_RUN_PLACEHOLDER %t.out
 //
 // Hits an assert in the Lower Work Group Scope Code pass on AMD:
-// XFAIL: rocm_amd
+// XFAIL: hip_amd
 
 // This test checks correctness of compiling and running of application with
 // kernel lambdas containing kernel_handler arguments and w/o usage of
diff --git a/SYCL/SpecConstants/2020/non_native/gpu.cpp b/SYCL/SpecConstants/2020/non_native/gpu.cpp
@@ -2,9 +2,8 @@
 // UNSUPPORTED: cuda
 // CUDA is not compatible with SPIR.
 //
-// UNSUPPORTED: rocm_nvidia
-// UNSUPPORTED: rocm_amd
-// ROCm is not compatible with SPIR.
+// UNSUPPORTED: hip
+// HIP is not compatible with SPIR.
 
 // RUN: %clangxx -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice -Xsycl-target-backend=spir64_gen-unknown-unknown-sycldevice "-device *" %S/Inputs/common.cpp -o %t.out
 // RUN: %GPU_RUN_PLACEHOLDER %t.out
diff --git a/SYCL/USM/dep_events.cpp b/SYCL/USM/dep_events.cpp
@@ -12,9 +12,9 @@
 // RUN: %GPU_RUN_PLACEHOLDER %t1.out
 // RUN: %ACC_RUN_PLACEHOLDER %t1.out
 //
-// XFAIL: cuda || rocm
+// XFAIL: cuda || hip
 // TODO enable the test when cuda_piextUSMEnqueuePrefetch and
-// rocm_piextUSMEnqueuePrefetch starts handling flags
+// hip_piextUSMEnqueuePrefetch starts handling flags
 
 #include <CL/sycl.hpp>
 
diff --git a/SYCL/lit.cfg.py b/SYCL/lit.cfg.py
@@ -184,7 +184,11 @@
     lit_config.error("Unknown HIP platform '" + config.hip_platform + "' supported platforms are " + ', '.join(supported_hip_platforms))
 
 if config.sycl_be == "hip" and config.hip_platform == "AMD":
+    config.available_features.add('hip_amd')
     arch_flag = '-Xsycl-target-backend=amdgcn-amd-amdhsa-sycldevice --offload-arch=' + config.amd_arch
+elif config.sycl_be == "hip" and config.hip_platform == "NVIDIA":
+    config.available_features.add('hip_nvidia')
+    arch_flag = ""
 else:
     arch_flag = ""
 
