@@ -74,7 +74,7 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
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pred_disable);
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});
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});
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- q.wait_and_throw ();
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+ q.wait ();
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} catch (sycl::exception e) {
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std::cout << " SYCL exception caught: " << e.what ();
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return 1 ;
@@ -113,7 +113,6 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
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template <unsigned SIMDSize> int testUSM (queue q) {
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auto size = size_t {128 };
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- auto *vec_input = malloc_shared<int >(size, q);
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auto *vec_0 = malloc_shared<int >(size, q);
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auto *vec_1 = malloc_shared<int >(size, q);
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auto *vec_2 = malloc_shared<int >(size, q);
@@ -122,7 +121,6 @@ template <unsigned SIMDSize> int testUSM(queue q) {
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std::iota (vec_1, vec_1 + size, 0 );
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std::iota (vec_2, vec_2 + size, 0 );
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std::iota (vec_3, vec_3 + size, 0 );
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- std::iota (vec_input, vec_3 + size, 0 );
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try {
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q.submit ([&](handler &h) {
@@ -134,21 +132,21 @@ template <unsigned SIMDSize> int testUSM(queue q) {
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auto pred_disable = simd_mask<1 >(0 );
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auto data_0 =
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- lsc_block_load<int , SIMDSize>(vec_input + offset, pred_enable);
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+ lsc_block_load<int , SIMDSize>(vec_0 + offset, pred_enable);
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lsc_block_store<int , SIMDSize>(vec_0 + offset, data_0 * 2 ,
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pred_enable);
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auto data_1 =
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- lsc_block_load<int , SIMDSize>(vec_input + offset, pred_disable);
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+ lsc_block_load<int , SIMDSize>(vec_1 + offset, pred_disable);
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lsc_block_store<int , SIMDSize>(vec_1 + offset, data_1 * 2 ,
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pred_enable);
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auto data_2 =
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- lsc_block_load<int , SIMDSize>(vec_input + offset, pred_enable);
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+ lsc_block_load<int , SIMDSize>(vec_2 + offset, pred_enable);
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lsc_block_store<int , SIMDSize>(vec_2 + offset, data_2 * 2 ,
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pred_disable);
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auto data_3 =
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- lsc_block_load<int , SIMDSize>(vec_input + offset, pred_disable);
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+ lsc_block_load<int , SIMDSize>(vec_3 + offset, pred_disable);
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lsc_block_store<int , SIMDSize>(vec_3 + offset, data_3 * 2 ,
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pred_disable);
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});
@@ -160,7 +158,6 @@ template <unsigned SIMDSize> int testUSM(queue q) {
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sycl::free (vec_1, q);
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sycl::free (vec_2, q);
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sycl::free (vec_3, q);
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- sycl::free (vec_input, q);
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return 1 ;
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}
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@@ -192,7 +189,6 @@ template <unsigned SIMDSize> int testUSM(queue q) {
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sycl::free (vec_1, q);
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sycl::free (vec_2, q);
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sycl::free (vec_3, q);
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- sycl::free (vec_input, q);
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std::cout << " USM lsc predicate test " ;
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std::cout << (error != 0 ? " FAILED" : " passed" ) << std::endl;
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return error;
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