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v-klochkovv-klochkov
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Merge remote-tracking branch 'intel_llvm/sycl' into public_vklochkov_reduction_int4
2 parents 9b355ef + 33a2868 commit 0b2702b

19 files changed

+607
-79
lines changed

‎buildbot/dependency.py

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,12 +49,18 @@ def do_dependency(args):
4949
# fetch OpenCL headers
5050
ocl_header_dir = os.path.join(args.obj_dir, "OpenCL-Headers")
5151
if not os.path.isdir(ocl_header_dir):
52-
clone_cmd = ["git", "clone", "https://github.com/KhronosGroup/OpenCL-Headers", "OpenCL-Headers"]
52+
clone_cmd = ["git", "clone", "https://github.com/KhronosGroup/OpenCL-Headers",
53+
"OpenCL-Headers", "-b", "v2020.06.16"]
5354
subprocess.check_call(clone_cmd, cwd=args.obj_dir)
5455
else:
5556
fetch_cmd = ["git", "pull", "--ff", "--ff-only", "origin"]
5657
subprocess.check_call(fetch_cmd, cwd=ocl_header_dir)
5758

59+
# Workaround to unblock CI until KhronosGroup/OpenCL-ICD-Loader/pull/124
60+
# is submitted
61+
checkout_cmd = ["git", "checkout", "d1b936b72b9610626ecab8a991cec18348fba047"]
62+
subprocess.check_call(checkout_cmd, cwd=ocl_header_dir)
63+
5864
# fetch and build OpenCL ICD loader
5965
icd_loader_dir = os.path.join(args.obj_dir, "OpenCL-ICD-Loader")
6066
if not os.path.isdir(icd_loader_dir):

‎clang/include/clang/Basic/AttrDocs.td

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2418,6 +2418,26 @@ device kernel, the attribute is not ignored and it is propagated to the kernel.
24182418
[[intel::num_simd_work_items(N)]] void operator()() const {}
24192419
};
24202420

2421+
If the`` intel::reqd_work_group_size`` or ``cl::reqd_work_group_size``
2422+
attribute is specified on a declaration along with a
2423+
intel::num_simd_work_items attribute, the work group size attribute
2424+
arguments must all be evenly divisible by the argument specified in
2425+
the ``intel::num_simd_work_items`` attribute.
2426+
2427+
.. code-block:: c++
2428+
2429+
struct func {
2430+
[[intel::num_simd_work_items(4)]]
2431+
[[intel::reqd_work_group_size(64, 64, 64)]]
2432+
void operator()() const {}
2433+
};
2434+
2435+
struct bar {
2436+
[[intel::reqd_work_group_size(64, 64, 64)]]
2437+
[[intel::num_simd_work_items(4)]]
2438+
void operator()() const {}
2439+
};
2440+
24212441
}];
24222442
}
24232443

‎clang/include/clang/Basic/DiagnosticSemaKinds.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11212,6 +11212,9 @@ def err_sycl_invalid_accessor_property_list_template_param : Error<
1121211212
"%select{accessor_property_list|accessor_property_list pack argument|buffer_location}0 "
1121311213
"template parameter must be a "
1121411214
"%select{parameter pack|type|non-negative integer}1">;
11215+
def err_sycl_num_kernel_wrong_reqd_wg_size : Error<
11216+
"%0 attribute must evenly divide the work-group size for the %1 attribute">;
11217+
1121511218
def warn_sycl_pass_by_value_deprecated
1121611219
: Warning<"Passing kernel functions by value is deprecated in SYCL 2020">,
1121711220
InGroup<Sycl2020Compat>, ShowInSystemHeader;

‎clang/include/clang/Sema/Sema.h

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -13068,21 +13068,23 @@ void Sema::addIntelSingleArgAttr(Decl *D, const AttributeCommonInfo &CI,
1306813068
return;
1306913069
E = ICE.get();
1307013070
int32_t ArgInt = ArgVal.getSExtValue();
13071-
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelNumSimdWorkItems ||
13072-
CI.getParsedKind() == ParsedAttr::AT_IntelReqdSubGroupSize ||
13071+
if (CI.getParsedKind() == ParsedAttr::AT_IntelReqdSubGroupSize ||
1307313072
CI.getParsedKind() == ParsedAttr::AT_IntelFPGAMaxReplicates) {
1307413073
if (ArgInt <= 0) {
1307513074
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
1307613075
<< CI << /*positive*/ 0;
1307713076
return;
1307813077
}
1307913078
}
13080-
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim) {
13079+
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim ||
13080+
CI.getParsedKind() == ParsedAttr::AT_SYCLIntelNumSimdWorkItems) {
1308113081
if (ArgInt < 0) {
1308213082
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
1308313083
<< CI << /*non-negative*/ 1;
1308413084
return;
1308513085
}
13086+
}
13087+
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim) {
1308613088
if (ArgInt > 3) {
1308713089
Diag(E->getBeginLoc(), diag::err_attribute_argument_out_of_range)
1308813090
<< CI << 0 << 3 << E->getSourceRange();

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8269,6 +8269,32 @@ static void addArgs(ArgStringList &DstArgs, const llvm::opt::ArgList &Alloc,
82698269
}
82708270
}
82718271

8272+
// Partially copied from clang/lib/Frontend/CompilerInvocation.cpp
8273+
static std::string getSYCLPostLinkOptimizationLevel(const ArgList &Args) {
8274+
if (Arg *A = Args.getLastArg(options::OPT_O_Group)) {
8275+
if (A->getOption().matches(options::OPT_O0))
8276+
return "-O0";
8277+
8278+
if (A->getOption().matches(options::OPT_Ofast))
8279+
return "-O3";
8280+
8281+
assert(A->getOption().matches(options::OPT_O));
8282+
8283+
StringRef S(A->getValue());
8284+
if (S == "g")
8285+
return "-O1";
8286+
8287+
// Options -O[1|2|3|s|z] are passed as they are. '-O0' is handled earlier.
8288+
std::array<char, 5> AcceptedOptions = {'1', '2', '3', 's', 'z'};
8289+
if (std::any_of(AcceptedOptions.begin(), AcceptedOptions.end(),
8290+
[=](char c) { return c == S[0]; }))
8291+
return std::string("-O") + S[0];
8292+
}
8293+
8294+
// The default for SYCL device code optimization
8295+
return "-O2";
8296+
}
8297+
82728298
// sycl-post-link tool normally outputs a file table (see the tool sources for
82738299
// format description) which lists all the other output files associated with
82748300
// the device LLVMIR bitcode. This is basically a triple of bitcode, symbols
@@ -8325,6 +8351,8 @@ void SYCLPostLink::ConstructJob(Compilation &C, const JobAction &JA,
83258351
options::OPT_fno_sycl_device_code_lower_esimd, false))
83268352
addArgs(CmdArgs, TCArgs, {"-lower-esimd"});
83278353
}
8354+
addArgs(CmdArgs, TCArgs,
8355+
{StringRef(getSYCLPostLinkOptimizationLevel(TCArgs))});
83288356
// specialization constants processing is mandatory
83298357
auto *SYCLPostLink = llvm::dyn_cast<SYCLPostLinkJobAction>(&JA);
83308358
if (SYCLPostLink && SYCLPostLink->getRTSetsSpecConstants())

‎clang/lib/Sema/SemaDeclAttr.cpp

Lines changed: 84 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -3130,26 +3130,53 @@ static void handleWorkGroupSize(Sema &S, Decl *D, const ParsedAttr &AL) {
31303130
return;
31313131
}
31323132

3133-
if (WorkGroupAttr *ExistingAttr = D->getAttr<WorkGroupAttr>()) {
3134-
ASTContext &Ctx = S.getASTContext();
3135-
Optional<llvm::APSInt> XDimVal = XDimExpr->getIntegerConstantExpr(Ctx);
3136-
Optional<llvm::APSInt> YDimVal = YDimExpr->getIntegerConstantExpr(Ctx);
3137-
Optional<llvm::APSInt> ZDimVal = ZDimExpr->getIntegerConstantExpr(Ctx);
3138-
Optional<llvm::APSInt> ExistingXDimVal = ExistingAttr->getXDimVal(Ctx);
3139-
Optional<llvm::APSInt> ExistingYDimVal = ExistingAttr->getYDimVal(Ctx);
3140-
Optional<llvm::APSInt> ExistingZDimVal = ExistingAttr->getZDimVal(Ctx);
3141-
3142-
// Compare attribute arguments value and warn for a mismatch.
3143-
if (ExistingXDimVal != XDimVal || ExistingYDimVal != YDimVal ||
3144-
ExistingZDimVal != ZDimVal) {
3145-
S.Diag(AL.getLoc(), diag::warn_duplicate_attribute) << AL;
3146-
S.Diag(ExistingAttr->getLocation(), diag::note_conflicting_attribute);
3133+
ASTContext &Ctx = S.getASTContext();
3134+
3135+
if (!XDimExpr->isValueDependent() && !YDimExpr->isValueDependent() &&
3136+
!ZDimExpr->isValueDependent()) {
3137+
llvm::APSInt XDimVal, YDimVal, ZDimVal;
3138+
ExprResult XDim = S.VerifyIntegerConstantExpression(XDimExpr, &XDimVal);
3139+
ExprResult YDim = S.VerifyIntegerConstantExpression(YDimExpr, &YDimVal);
3140+
ExprResult ZDim = S.VerifyIntegerConstantExpression(ZDimExpr, &ZDimVal);
3141+
3142+
if (XDim.isInvalid())
3143+
return;
3144+
XDimExpr = XDim.get();
3145+
3146+
if (YDim.isInvalid())
3147+
return;
3148+
YDimExpr = YDim.get();
3149+
3150+
if (ZDim.isInvalid())
3151+
return;
3152+
ZDimExpr = ZDim.get();
3153+
3154+
if (const auto *A = D->getAttr<SYCLIntelNumSimdWorkItemsAttr>()) {
3155+
int64_t NumSimdWorkItems =
3156+
A->getValue()->getIntegerConstantExpr(Ctx)->getSExtValue();
3157+
3158+
if (!(XDimVal.getZExtValue() % NumSimdWorkItems == 0 ||
3159+
YDimVal.getZExtValue() % NumSimdWorkItems == 0 ||
3160+
ZDimVal.getZExtValue() % NumSimdWorkItems == 0)) {
3161+
S.Diag(A->getLocation(), diag::err_sycl_num_kernel_wrong_reqd_wg_size)
3162+
<< A << AL;
3163+
S.Diag(AL.getLoc(), diag::note_conflicting_attribute);
3164+
return;
3165+
}
3166+
}
3167+
if (const auto *ExistingAttr = D->getAttr<WorkGroupAttr>()) {
3168+
// Compare attribute arguments value and warn for a mismatch.
3169+
if (ExistingAttr->getXDimVal(Ctx) != XDimVal ||
3170+
ExistingAttr->getYDimVal(Ctx) != YDimVal ||
3171+
ExistingAttr->getZDimVal(Ctx) != ZDimVal) {
3172+
S.Diag(AL.getLoc(), diag::warn_duplicate_attribute) << AL;
3173+
S.Diag(ExistingAttr->getLocation(), diag::note_conflicting_attribute);
3174+
}
31473175
}
3176+
if (!checkWorkGroupSizeValues(S, D, AL))
3177+
return;
31483178
}
31493179

3150-
if (!checkWorkGroupSizeValues(S, D, AL))
3151-
return;
3152-
31533180
S.addIntelTripleArgAttr<WorkGroupAttr>(D, AL, XDimExpr, YDimExpr, ZDimExpr);
31543181
}
31553182

@@ -3196,18 +3223,51 @@ static void handleSubGroupSize(Sema &S, Decl *D, const ParsedAttr &AL) {
31963223
}
31973224

31983225
// Handles num_simd_work_items.
3199-
static void handleNumSimdWorkItemsAttr(Sema &S, Decl *D, const ParsedAttr &A) {
3226+
static void handleNumSimdWorkItemsAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
32003227
if (D->isInvalidDecl())
32013228
return;
32023229

3203-
Expr *E = A.getArgAsExpr(0);
3230+
Expr *E = AL.getArgAsExpr(0);
32043231

32053232
if (D->getAttr<SYCLIntelNumSimdWorkItemsAttr>())
3206-
S.Diag(A.getLoc(), diag::warn_duplicate_attribute) << A;
3233+
S.Diag(AL.getLoc(), diag::warn_duplicate_attribute) << AL;
32073234

3208-
S.CheckDeprecatedSYCLAttributeSpelling(A);
3235+
S.CheckDeprecatedSYCLAttributeSpelling(AL);
3236+
3237+
if (!E->isValueDependent()) {
3238+
llvm::APSInt ArgVal;
3239+
ExprResult ICE = S.VerifyIntegerConstantExpression(E, &ArgVal);
32093240

3210-
S.addIntelSingleArgAttr<SYCLIntelNumSimdWorkItemsAttr>(D, A, E);
3241+
if (ICE.isInvalid())
3242+
return;
3243+
3244+
E = ICE.get();
3245+
int64_t NumSimdWorkItems = ArgVal.getSExtValue();
3246+
3247+
if (NumSimdWorkItems == 0) {
3248+
S.Diag(E->getExprLoc(), diag::err_attribute_argument_is_zero)
3249+
<< AL << E->getSourceRange();
3250+
return;
3251+
}
3252+
3253+
if (const auto *A = D->getAttr<ReqdWorkGroupSizeAttr>()) {
3254+
ASTContext &Ctx = S.getASTContext();
3255+
Optional<llvm::APSInt> XDimVal = A->getXDimVal(Ctx);
3256+
Optional<llvm::APSInt> YDimVal = A->getYDimVal(Ctx);
3257+
Optional<llvm::APSInt> ZDimVal = A->getZDimVal(Ctx);
3258+
3259+
if (!(XDimVal->getZExtValue() % NumSimdWorkItems == 0 ||
3260+
YDimVal->getZExtValue() % NumSimdWorkItems == 0 ||
3261+
ZDimVal->getZExtValue() % NumSimdWorkItems == 0)) {
3262+
S.Diag(AL.getLoc(), diag::err_sycl_num_kernel_wrong_reqd_wg_size)
3263+
<< AL << A;
3264+
S.Diag(A->getLocation(), diag::note_conflicting_attribute);
3265+
return;
3266+
}
3267+
}
3268+
}
3269+
3270+
S.addIntelSingleArgAttr<SYCLIntelNumSimdWorkItemsAttr>(D, AL, E);
32113271
}
32123272

32133273
// Handles use_stall_enable_clusters
@@ -5967,14 +6027,13 @@ void Sema::addSYCLIntelPipeIOAttr(Decl *D, const AttributeCommonInfo &Attr,
59676027
Optional<llvm::APSInt> ArgVal = E->getIntegerConstantExpr(getASTContext());
59686028
if (!ArgVal) {
59696029
Diag(E->getExprLoc(), diag::err_attribute_argument_type)
5970-
<< Attr.getAttrName() << AANT_ArgumentIntegerConstant
5971-
<< E->getSourceRange();
6030+
<< Attr << AANT_ArgumentIntegerConstant << E->getSourceRange();
59726031
return;
59736032
}
59746033
int32_t ArgInt = ArgVal->getSExtValue();
59756034
if (ArgInt < 0) {
59766035
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
5977-
<< Attr.getAttrName() << /*non-negative*/ 1;
6036+
<< Attr << /*non-negative*/ 1;
59786037
return;
59796038
}
59806039
}

‎clang/test/Driver/sycl-device-lib.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@
121121
// RUN: | FileCheck %s -check-prefix=SYCL_LLVM_LINK_NO_DEVICE_LIB
122122
// SYCL_LLVM_LINK_NO_DEVICE_LIB: clang{{.*}} "-cc1" {{.*}} "-fsycl-is-device"
123123
// SYCL_LLVM_LINK_NO_DEVICE_LIB-NOT: llvm-link{{.*}} "-only-needed"
124-
// SYCL_LLVM_LINK_NO_DEVICE_LIB: sycl-post-link{{.*}} "-symbols" "-split-esimd" "-spec-const=rt" "-o" "{{.*}}.table" "{{.*}}.bc"
124+
// SYCL_LLVM_LINK_NO_DEVICE_LIB: sycl-post-link{{.*}} "-symbols" "-split-esimd" "-O2" "-spec-const=rt" "-o" "{{.*}}.table" "{{.*}}.bc"
125125

126126
/// ###########################################################################
127127
/// test llvm-link behavior for special user input whose filename resembles SYCL device library

‎clang/test/Driver/sycl-intelfpga-aoco-win.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@
4747
// CHK-FPGA-AOCO: llvm-link{{.*}} "[[OUTLIB]]" "-o" "[[LINKEDBC:.+\.bc]]"
4848
// CHK-FPGA-AOCO: sycl-post-link
4949
// CHK-FPGA-AOCO-NOT: -split-esimd
50-
// CHK-FPGA-AOCO: "-ir-output-only" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.bc]]" "[[LINKEDBC]]"
50+
// CHK-FPGA-AOCO: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.bc]]" "[[LINKEDBC]]"
5151
// CHK-FPGA-AOCO: llvm-spirv{{.*}} "-o" "[[TARGSPV:.+\.spv]]" {{.*}} "[[PLINKEDBC]]"
5252
// CHK-FPGA-AOCO: clang-offload-bundler{{.*}} "-type=aoo" "-targets=sycl-fpga_aoco-intel-unknown-sycldevice" "-inputs=[[INPUTLIB]]" "-outputs=[[AOCOLIST:.+\.txt]]" "-unbundle"
5353
// CHK-FPGA-AOCO: aoc{{.*}} "-o" "[[AOCXOUT:.+\.aocx]]" "[[TARGSPV]]" "-library-list=[[AOCOLIST]]" "-sycl"

‎clang/test/Driver/sycl-intelfpga-aoco.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@
8585
// CHK-FPGA-AOCO: llvm-link{{.*}} "[[OUTLIB]]" "-o" "[[LINKEDBC:.+\.bc]]"
8686
// CHK-FPGA-AOCO: sycl-post-link
8787
// CHK-FPGA-AOCO-NOT: "-split-esimd"
88-
// CHK-FPGA-AOCO: "-ir-output-only" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.bc]]" "[[LINKEDBC]]"
88+
// CHK-FPGA-AOCO: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.bc]]" "[[LINKEDBC]]"
8989
// CHK-FPGA-AOCO: llvm-spirv{{.*}} "-o" "[[TARGSPV:.+\.spv]]" {{.*}} "[[PLINKEDBC]]"
9090
// CHK-FPGA-AOCO: clang-offload-bundler{{.*}} "-type=aoo" "-targets=sycl-fpga_aoco-intel-unknown-sycldevice" "-inputs=[[INPUTLIB]]" "-outputs=[[AOCOLIST:.+\.txt]]" "-unbundle"
9191
// CHK-FPGA-AOCO: aoc{{.*}} "-o" "[[AOCXOUT:.+\.aocx]]" "[[TARGSPV]]" "-library-list=[[AOCOLIST]]" "-sycl"

‎clang/test/Driver/sycl-offload-intelfpga.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@
3333
// CHK-FPGA-LINK: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]"
3434
// CHK-FPGA-LINK: sycl-post-link
3535
// CHK-FPGA-LINK-NOT: -split-esimd
36-
// CHK-FPGA-LINK: "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
36+
// CHK-FPGA-LINK: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
3737
// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-debug-info-version=legacy" "-spirv-allow-extra-diexpressions" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2]]"
3838
// CHK-FPGA-EARLY: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl"
3939
// CHK-FPGA-IMAGE: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocx]]" "[[OUTPUT3]]" "-sycl"
@@ -67,7 +67,7 @@
6767
// CHK-FPGA-LINK-WIN: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]"
6868
// CHK-FPGA-LINK-WIN: sycl-post-link
6969
// CHK-FPGA-LINK-WIN-NOT: -split-esimd
70-
// CHK-FPGA-LINK-WIN: "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
70+
// CHK-FPGA-LINK-WIN: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
7171
// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-debug-info-version=legacy" "-spirv-allow-extra-diexpressions" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2]]"
7272
// CHK-FPGA-LINK-WIN: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl"
7373
// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl"
@@ -132,7 +132,7 @@
132132
// CHK-FPGA: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_BC:.+\.bc]]"
133133
// CHK-FPGA: sycl-post-link
134134
// CHK-FPGA-NOT: -split-esimd
135-
// CHK-FPGA: "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT3_BC:.+\.bc]]" "[[OUTPUT2_BC]]"
135+
// CHK-FPGA: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT3_BC:.+\.bc]]" "[[OUTPUT2_BC]]"
136136
// CHK-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT5:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-debug-info-version=legacy" "-spirv-allow-extra-diexpressions" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT3_BC]]"
137137
// CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-fpga_dep" {{.*}} "-outputs=[[DEPFILE:.+\.d]]" "-unbundle"
138138
// CHK-FPGA: aoc{{.*}} "-o" "[[OUTPUT6:.+\.aocx]]" "[[OUTPUT5]]" "-sycl" "-dep-files=[[DEPFILE]]"
@@ -186,7 +186,7 @@
186186
// CHK-FPGA-AOCX-SRC: llvm-link{{.*}} "[[DEVICEBC]]" "-o" "[[LLVMLINKOUT:.+\.bc]]" "--suppress-warnings"
187187
// CHK-FPGA-AOCX-SRC: sycl-post-link
188188
// CHK-FPGA-AOCX-SRC-NOT: -split-esimd
189-
// CHK-FPGA-AOCX-SRC: "-ir-output-only" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]]
189+
// CHK-FPGA-AOCX-SRC: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]]
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// CHK-FPGA-AOCX-SRC: llvm-spirv{{.*}} "-o" "[[LLVMSPVOUT:.+\.spv]]" {{.*}} "[[POSTLINKOUT]]"
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// CHK-FPGA-AOCX-SRC: aoc{{.*}} "-o" "[[AOCOUT:.+\.aocx]]" "[[LLVMSPVOUT]]" "-sycl"
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// CHK-FPGA-AOCX-SRC: clang-offload-wrapper{{.*}} "-o=[[WRAPOUTSRC:.+.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "[[AOCOUT]]"
@@ -209,7 +209,7 @@
209209
// CHK-FPGA-AOCX-OBJ: llvm-link{{.*}} "[[DEVICEOBJ]]" "-o" "[[LLVMLINKOUT:.+\.bc]]" "--suppress-warnings"
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// CHK-FPGA-AOCX-OBJ: sycl-post-link
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// CHK-FPGA-AOCX-OBJ-NOT: -split-esimd
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// CHK-FPGA-AOCX-OBJ: "-ir-output-only" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]]
212+
// CHK-FPGA-AOCX-OBJ: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]]
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// CHK-FPGA-AOCX-OBJ: llvm-spirv{{.*}} "-o" "[[LLVMSPVOUT:.+\.spv]]" {{.*}} "[[POSTLINKOUT]]"
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// CHK-FPGA-AOCX-OBJ: aoc{{.*}} "-o" "[[AOCOUT:.+\.aocx]]" "[[LLVMSPVOUT]]" "-sycl"
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// CHK-FPGA-AOCX-OBJ: clang-offload-wrapper{{.*}} "-o=[[WRAPOUTSRC:.+.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "[[AOCOUT]]"

‎clang/test/Driver/sycl-offload.c

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Original file line numberDiff line numberDiff line change
@@ -903,3 +903,33 @@
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// CHECK-STD-OVR: clang{{.*}} "-fsyntax-only" {{.*}} "-std=c++14"
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// CHECK-STD-OVR: clang{{.*}} "-emit-obj" {{.*}} "-std=c++14"
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// CHECK-STD-OVR-NOT: clang{{.*}} "-std=c++17"
906+
907+
// Check sycl-post-link optimization level.
908+
// Default is O2
909+
// RUN: %clang -### -fsycl %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O2
910+
// RUN: %clang_cl -### -fsycl %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O2
911+
// Common options for %clang and %clang_cl
912+
// RUN: %clang -### -fsycl -O1 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O1
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// RUN: %clang_cl -### -fsycl /O1 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-Os
914+
// RUN: %clang -### -fsycl -O2 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O2
915+
// RUN: %clang_cl -### -fsycl /O2 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O2
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// RUN: %clang -### -fsycl -Os %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-Os
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// RUN: %clang_cl -### -fsycl /Os %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-Os
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// %clang options
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// RUN: %clang -### -fsycl -O0 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O0
920+
// RUN: %clang -### -fsycl -Ofast %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O3
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// RUN: %clang -### -fsycl -O3 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O3
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// RUN: %clang -### -fsycl -Oz %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-Oz
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// RUN: %clang -### -fsycl -Og %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O1
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// %clang_cl options
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// RUN: %clang_cl -### -fsycl /Od %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O0
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// RUN: %clang_cl -### -fsycl /Ot %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O2
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// only the last option is considered
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// RUN: %clang -### -fsycl -O2 -O1 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O1
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// RUN: %clang_cl -### -fsycl /O2 /O1 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-Os
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// CHK-POST-LINK-OPT-LEVEL-O0: sycl-post-link{{.*}} "-O0"
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// CHK-POST-LINK-OPT-LEVEL-O1: sycl-post-link{{.*}} "-O1"
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// CHK-POST-LINK-OPT-LEVEL-O2: sycl-post-link{{.*}} "-O2"
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// CHK-POST-LINK-OPT-LEVEL-O3: sycl-post-link{{.*}} "-O3"
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// CHK-POST-LINK-OPT-LEVEL-Os: sycl-post-link{{.*}} "-Os"
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// CHK-POST-LINK-OPT-LEVEL-Oz: sycl-post-link{{.*}} "-Oz"

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