Merge remote-tracking branch 'intel_llvm/sycl' into ww08

Author: vmaksimo

buildbot/dependency.conf

@@ -4,8 +4,8 @@ ocl_cpu_rt_ver=2020.11.11.0.04
 # https://github.com/intel/llvm/releases/download/2020-WW45/win-oclcpuexp-2020.11.11.0.04_rel.zip
 ocl_cpu_rt_ver_win=2020.11.11.0.04
 # Same GPU driver supports Level Zero and OpenCL
-# https://github.com/intel/compute-runtime/releases/tag/21.04.18912
-ocl_gpu_rt_ver=21.04.18912
+# https://github.com/intel/compute-runtime/releases/tag/21.07.19042
+ocl_gpu_rt_ver=21.07.19042
 # Same GPU driver supports Level Zero and OpenCL
 # https://downloadmirror.intel.com/30148/a08/igfx_win10_100.9168.zip
 ocl_gpu_rt_ver_win=27.20.100.9168
@@ -30,7 +30,7 @@ ocloc_ver_win=27.20.100.9168
 [DRIVER VERSIONS]
 cpu_driver_lin=2020.11.11.0.04
 cpu_driver_win=2020.11.11.0.04
-gpu_driver_lin=21.04.18912
+gpu_driver_lin=21.07.19042
 gpu_driver_win=27.20.100.9168
 fpga_driver_lin=2020.11.11.0.04
 fpga_driver_win=2020.11.11.0.04

buildbot/dependency.py

@@ -49,12 +49,18 @@ def do_dependency(args):
     # fetch OpenCL headers
     ocl_header_dir = os.path.join(args.obj_dir, "OpenCL-Headers")
     if not os.path.isdir(ocl_header_dir):
-        clone_cmd = ["git", "clone", "https://github.com/KhronosGroup/OpenCL-Headers", "OpenCL-Headers"]
+        clone_cmd = ["git", "clone", "https://github.com/KhronosGroup/OpenCL-Headers",
+                     "OpenCL-Headers", "-b", "v2020.06.16"]
         subprocess.check_call(clone_cmd, cwd=args.obj_dir)
     else:
         fetch_cmd = ["git", "pull", "--ff", "--ff-only", "origin"]
         subprocess.check_call(fetch_cmd, cwd=ocl_header_dir)
 
+    # Workaround to unblock CI until KhronosGroup/OpenCL-ICD-Loader/pull/124
+    # is submitted
+    checkout_cmd = ["git", "checkout", "d1b936b72b9610626ecab8a991cec18348fba047"]
+    subprocess.check_call(checkout_cmd, cwd=ocl_header_dir)
+
     # fetch and build OpenCL ICD loader
     icd_loader_dir = os.path.join(args.obj_dir, "OpenCL-ICD-Loader")
     if not os.path.isdir(icd_loader_dir):

clang/include/clang/Basic/Attr.td

@@ -1395,7 +1395,7 @@ def IntelReqdSubGroupSize: InheritableAttr {
   let Spellings = [GNU<"intel_reqd_sub_group_size">,
                    CXX11<"intel", "reqd_sub_group_size">];
   let Args = [ExprArgument<"Value">];
-  let Subjects = SubjectList<[Function, CXXMethod], ErrorDiag>;
+  let Subjects = SubjectList<[Function], ErrorDiag>;
   let Documentation = [IntelReqdSubGroupSizeDocs];
   let LangOpts = [OpenCL, SYCLIsDevice, SYCLIsHost];
 }

clang/include/clang/Sema/Sema.h

@@ -10213,6 +10213,16 @@ class Sema final {
   template <typename AttrType>
   void addIntelTripleArgAttr(Decl *D, const AttributeCommonInfo &CI,
                              Expr *XDimExpr, Expr *YDimExpr, Expr *ZDimExpr);
+  void AddIntelReqdSubGroupSize(Decl *D, const AttributeCommonInfo &CI,
+                                Expr *E);
+  IntelReqdSubGroupSizeAttr *
+  MergeIntelReqdSubGroupSizeAttr(Decl *D, const IntelReqdSubGroupSizeAttr &A);
+  void AddSYCLIntelNumSimdWorkItemsAttr(Decl *D, const AttributeCommonInfo &CI,
+                                        Expr *E);
+  SYCLIntelNumSimdWorkItemsAttr *
+  MergeSYCLIntelNumSimdWorkItemsAttr(Decl *D,
+                                     const SYCLIntelNumSimdWorkItemsAttr &A);
+
   /// AddAlignedAttr - Adds an aligned attribute to a particular declaration.
   void AddAlignedAttr(Decl *D, const AttributeCommonInfo &CI, Expr *E,
                       bool IsPackExpansion);
@@ -13071,16 +13081,14 @@ void Sema::addIntelSingleArgAttr(Decl *D, const AttributeCommonInfo &CI,
       return;
     E = ICE.get();
     int32_t ArgInt = ArgVal.getSExtValue();
-    if (CI.getParsedKind() == ParsedAttr::AT_IntelReqdSubGroupSize ||
-        CI.getParsedKind() == ParsedAttr::AT_IntelFPGAMaxReplicates) {
+    if (CI.getParsedKind() == ParsedAttr::AT_IntelFPGAMaxReplicates) {
       if (ArgInt <= 0) {
         Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
             << CI << /*positive*/ 0;
         return;
       }
     }
-    if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim ||
-        CI.getParsedKind() == ParsedAttr::AT_SYCLIntelNumSimdWorkItems) {
+    if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim) {
       if (ArgInt < 0) {
         Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
             << CI << /*non-negative*/ 1;

clang/lib/CodeGen/BackendUtil.cpp

@@ -28,7 +28,6 @@
 #include "llvm/CodeGen/RegAllocRegistry.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
-#include "llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/IRPrintingPasses.h"
 #include "llvm/IR/LegacyPassManager.h"
@@ -42,7 +41,6 @@
 #include "llvm/Passes/PassBuilder.h"
 #include "llvm/Passes/PassPlugin.h"
 #include "llvm/Passes/StandardInstrumentations.h"
-#include "llvm/SYCLLowerIR/LowerESIMD.h"
 #include "llvm/Support/BuryPointer.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/MemoryBuffer.h"
@@ -840,25 +838,6 @@ void EmitAssemblyHelper::CreatePasses(legacy::PassManager &MPM,
 
   PMBuilder.populateFunctionPassManager(FPM);
   PMBuilder.populateModulePassManager(MPM);
-
-  // Customize the tail of the module passes list for the ESIMD extension.
-  if (LangOpts.SYCLIsDevice && LangOpts.SYCLExplicitSIMD &&
-      CodeGenOpts.OptimizationLevel != 0) {
-    MPM.add(createESIMDLowerVecArgPass());
-    MPM.add(createESIMDLowerLoadStorePass());
-    MPM.add(createSROAPass());
-    MPM.add(createEarlyCSEPass(true));
-    MPM.add(createInstructionCombiningPass());
-    MPM.add(createDeadCodeEliminationPass());
-    MPM.add(createFunctionInliningPass(
-        CodeGenOpts.OptimizationLevel, CodeGenOpts.OptimizeSize,
-        (!CodeGenOpts.SampleProfileFile.empty() &&
-         CodeGenOpts.PrepareForThinLTO)));
-    MPM.add(createSROAPass());
-    MPM.add(createEarlyCSEPass(true));
-    MPM.add(createInstructionCombiningPass());
-    MPM.add(createDeadCodeEliminationPass());
-  }
 }
 
 static void setCommandLineOpts(const CodeGenOptions &CodeGenOpts) {
@@ -955,11 +934,6 @@ void EmitAssemblyHelper::EmitAssembly(BackendAction Action,
   PerFunctionPasses.add(
       createTargetTransformInfoWrapperPass(getTargetIRAnalysis()));
 
-  // ESIMD extension always requires lowering of certain IR constructs, such as
-  // ESIMD C++ intrinsics, as the last FE step.
-  if (LangOpts.SYCLIsDevice && LangOpts.SYCLExplicitSIMD)
-    PerModulePasses.add(createSYCLLowerESIMDPass());
-
   CreatePasses(PerModulePasses, PerFunctionPasses);
 
   legacy::PassManager CodeGenPasses;
@@ -977,9 +951,6 @@ void EmitAssemblyHelper::EmitAssembly(BackendAction Action,
       !LangOpts.SYCLExplicitSIMD && LangOpts.EnableDAEInSpirKernels)
     PerModulePasses.add(createDeadArgEliminationSYCLPass());
 
-  if (LangOpts.SYCLIsDevice && LangOpts.SYCLExplicitSIMD)
-    PerModulePasses.add(createGenXSPIRVWriterAdaptorPass());
-
   switch (Action) {
   case Backend_EmitNothing:
     break;

clang/lib/CodeGen/CMakeLists.txt

@@ -27,14 +27,6 @@ set(LLVM_LINK_COMPONENTS
   TransformUtils
   )
 
-
-get_property(LLVMGenXIntrinsics_SOURCE_DIR GLOBAL PROPERTY LLVMGenXIntrinsics_SOURCE_PROP)
-get_property(LLVMGenXIntrinsics_BINARY_DIR GLOBAL PROPERTY LLVMGenXIntrinsics_BINARY_PROP)
-
-include_directories(
-  ${LLVMGenXIntrinsics_SOURCE_DIR}/GenXIntrinsics/include
-  ${LLVMGenXIntrinsics_BINARY_DIR}/GenXIntrinsics/include)
-
 add_clang_library(clangCodeGen
   BackendUtil.cpp
   CGAtomic.cpp
@@ -96,14 +88,9 @@ add_clang_library(clangCodeGen
   TargetInfo.cpp
   VarBypassDetector.cpp
 
-  ADDITIONAL_HEADER_DIRS
-  ${LLVMGenXIntrinsics_SOURCE_DIR}/GenXIntrinsics/include
-  ${LLVMGenXIntrinsics_BINARY_DIR}/GenXIntrinsics/include
-
   DEPENDS
   ${codegen_deps}
   intrinsics_gen
-  LLVMGenXIntrinsics
 
   LINK_LIBS
   clangAnalysis
@@ -112,5 +99,4 @@ add_clang_library(clangCodeGen
   clangFrontend
   clangLex
   clangSerialization
-  LLVMGenXIntrinsics
   )

clang/lib/CodeGen/CodeGenModule.cpp

@@ -1627,7 +1627,9 @@ void CodeGenModule::GenOpenCLArgMetadata(llvm::Function *Fn,
             CGF->Builder.getInt1(parm->hasAttr<SYCLSimdAccessorPtrAttr>())));
     }
 
-  if (LangOpts.SYCLIsDevice && !LangOpts.SYCLExplicitSIMD)
+  bool IsEsimdFunction = FD && FD->hasAttr<SYCLSimdAttr>();
+
+  if (LangOpts.SYCLIsDevice && !IsEsimdFunction)
     Fn->setMetadata("kernel_arg_buffer_location",
                     llvm::MDNode::get(VMContext, argSYCLBufferLocationAttr));
   else {
@@ -1641,7 +1643,7 @@ void CodeGenModule::GenOpenCLArgMetadata(llvm::Function *Fn,
                     llvm::MDNode::get(VMContext, argBaseTypeNames));
     Fn->setMetadata("kernel_arg_type_qual",
                     llvm::MDNode::get(VMContext, argTypeQuals));
-    if (FD && FD->hasAttr<SYCLSimdAttr>())
+    if (IsEsimdFunction)
       Fn->setMetadata("kernel_arg_accessor_ptr",
                       llvm::MDNode::get(VMContext, argESIMDAccPtrs));
     if (getCodeGenOpts().EmitOpenCLArgMetadata)

clang/lib/Driver/ToolChains/Clang.cpp

@@ -8367,7 +8367,7 @@ void SYCLPostLink::ConstructJob(Compilation &C, const JobAction &JA,
                        options::OPT_fno_sycl_device_code_split_esimd, true))
       addArgs(CmdArgs, TCArgs, {"-split-esimd"});
     if (TCArgs.hasFlag(options::OPT_fsycl_device_code_lower_esimd,
-                       options::OPT_fno_sycl_device_code_lower_esimd, false))
+                       options::OPT_fno_sycl_device_code_lower_esimd, true))
       addArgs(CmdArgs, TCArgs, {"-lower-esimd"});
   }
   addArgs(CmdArgs, TCArgs,

clang/lib/Sema/SemaDecl.cpp

@@ -2618,6 +2618,10 @@ static bool mergeDeclAttribute(Sema &S, NamedDecl *D,
     NewAttr = S.mergeEnforceTCBAttr(D, *TCBA);
   else if (const auto *TCBLA = dyn_cast<EnforceTCBLeafAttr>(Attr))
     NewAttr = S.mergeEnforceTCBLeafAttr(D, *TCBLA);
+  else if (const auto *A = dyn_cast<IntelReqdSubGroupSizeAttr>(Attr))
+    NewAttr = S.MergeIntelReqdSubGroupSizeAttr(D, *A);
+  else if (const auto *A = dyn_cast<SYCLIntelNumSimdWorkItemsAttr>(Attr))
+    NewAttr = S.MergeSYCLIntelNumSimdWorkItemsAttr(D, *A);
   else if (Attr->shouldInheritEvenIfAlreadyPresent() || !DeclHasAttr(D, Attr))
     NewAttr = cast<InheritableAttr>(Attr->clone(S.Context));