@@ -24,38 +24,38 @@ $_ZTS11load_kernelIiE = comdat any
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@__spirv_BuiltInGlobalInvocationId = external dso_local local_unnamed_addr addrspace (1 ) constant <3 x i64 >, align 32
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; Function Attrs: convergent norecurse
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- define weak_odr dso_local spir_kernel void @_ZTSN2cl4sycl6detail19__pf_kernel_wrapperI11load_kernelIiEEE(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_, i32 addrspace(1)* %_arg_1, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_2, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_3, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_4, i32 addrspace(1)* %_arg_5, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_7, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_8, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_9) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !4 {
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+ define weak_odr dso_local spir_kernel void @_ZTSN2cl4sycl6detail19__pf_kernel_wrapperI11load_kernelIiEEE (ptr byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_ , ptr addrspace (1 ) %_arg_1 , ptr byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_2 , ptr byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_3 , ptr byval (%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" ) align 8 %_arg_4 , ptr addrspace (1 ) %_arg_5 , ptr byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_7 , ptr byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_8 , ptr byval (%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" ) align 8 %_arg_9 ) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !4 {
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entry:
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; CHECK-LABEL: _ZTSN2cl4sycl6detail19__pf_kernel_wrapperI11load_kernelIiEEE(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: call void @__itt_offload_wi_start_wrapper()
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- %0 = getelementptr inbounds %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" , % "class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" * %_arg_ , i64 0 , i32 0 , i32 0 , i64 0
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- %1 = addrspacecast i64* %0 to i64 addrspace (4 )*
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- %2 = load i64 , i64 addrspace (4 )* %1 , align 8
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- %3 = load <3 x i64 >, < 3 x i64 > addrspace (4 )* addrspacecast (< 3 x i64 > addrspace (1 )* @__spirv_BuiltInGlobalInvocationId to < 3 x i64 > addrspace (4 )* ), align 32 , !noalias !5
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+ %0 = getelementptr inbounds %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" , ptr %_arg_ , i64 0 , i32 0 , i32 0 , i64 0
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+ %1 = addrspacecast i64* %0 to ptr addrspace (4 )
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+ %2 = load i64 , ptr addrspace (4 ) %1 , align 8
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+ %3 = load <3 x i64 >, ptr addrspace (4 ) addrspacecast (ptr addrspace (1 ) @__spirv_BuiltInGlobalInvocationId to ptr addrspace (4 )), align 32 , !noalias !5
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%4 = extractelement <3 x i64 > %3 , i64 0
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%cmp.not.i = icmp ult i64 %4 , %2
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br i1 %cmp.not.i , label %if.end.i , label %_ZZN2cl4sycl7handler24parallel_for_lambda_implI11load_kernelIiEZZ9load_testIiEvNS0_5queueEmENKUlRS1_E_clES7_EUlNS0_4itemILi1ELb1EEEE_Li1EEEvNS0_5rangeIXT1_EEET0_ENKUlSA_E_clESA_.exit
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if.end.i: ; preds = %entry
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- %5 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" , % "class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" * %_arg_9 , i64 0 , i32 0 , i32 0 , i64 0
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- %6 = addrspacecast i64* %5 to i64 addrspace (4 )*
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- %7 = load i64 , i64 addrspace (4 )* %6 , align 8
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- %add.ptr.i = getelementptr inbounds i32 , i32 addrspace (1 )* %_arg_5 , i64 %7
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- %8 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" , % "class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" * %_arg_4 , i64 0 , i32 0 , i32 0 , i64 0
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- %9 = addrspacecast i64* %8 to i64 addrspace (4 )*
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- %10 = load i64 , i64 addrspace (4 )* %9 , align 8
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- %add.ptr.i34 = getelementptr inbounds i32 , i32 addrspace (1 )* %_arg_1 , i64 %10
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- ; CHECK: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast i32 addrspace(1)* %[[ATOMIC_ARG_1:[0-9a-zA-Z._]+]] to i8 addrspace(4)*
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- ; CHECK-NEXT: call void @__itt_offload_atomic_op_start(i8 addrspace(4)* [[ARG_ASCAST]], i32 0, i32 0)
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- ; CHECK-NEXT: {{.*}}__spirv_AtomicLoad{{.*}}(i32 addrspace(1)* %[[ATOMIC_ARG_1]],{{.*}}, i32 896
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- ; CHECK-NEXT: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast i32 addrspace(1)* %[[ATOMIC_ARG_1]] to i8 addrspace(4)*
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- ; CHECK-NEXT: call void @__itt_offload_atomic_op_finish(i8 addrspace(4)* [[ARG_ASCAST]], i32 0, i32 0)
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- %call3.i.i.i.i = tail call spir_func i32 @_Z18__spirv_AtomicLoadPU3AS1KiN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE (i32 addrspace (1 )* %add.ptr.i34 , i32 1 , i32 896 ) #2
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- call spir_func void @__synthetic_spir_fun_call (i32 addrspace (1 )* %add.ptr.i34 )
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- %ptridx.i.i.i = getelementptr inbounds i32 , i32 addrspace (1 )* %add.ptr.i , i64 %4
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- %ptridx.ascast.i.i.i = addrspacecast i32 addrspace (1 )* %ptridx.i.i.i to i32 addrspace (4 )*
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- store i32 %call3.i.i.i.i , i32 addrspace (4 )* %ptridx.ascast.i.i.i , align 4 , !tbaa !14
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+ %5 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" , ptr %_arg_9 , i64 0 , i32 0 , i32 0 , i64 0
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+ %6 = addrspacecast i64* %5 to ptr addrspace (4 )
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+ %7 = load i64 , ptr addrspace (4 ) %6 , align 8
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+ %add.ptr.i = getelementptr inbounds i32 , ptr addrspace (1 ) %_arg_5 , i64 %7
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+ %8 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" , ptr %_arg_4 , i64 0 , i32 0 , i32 0 , i64 0
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+ %9 = addrspacecast i64* %8 to ptr addrspace (4 )
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+ %10 = load i64 , ptr addrspace (4 ) %9 , align 8
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+ %add.ptr.i34 = getelementptr inbounds i32 , ptr addrspace (1 ) %_arg_1 , i64 %10
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+ ; CHECK: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast ptr addrspace(1) %[[ATOMIC_ARG_1:[0-9a-zA-Z._]+]] to ptr addrspace(4)
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+ ; CHECK-NEXT: call void @__itt_offload_atomic_op_start(ptr addrspace(4) [[ARG_ASCAST]], i32 0, i32 0)
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+ ; CHECK-NEXT: {{.*}}__spirv_AtomicLoad{{.*}}(ptr addrspace(1) %[[ATOMIC_ARG_1]],{{.*}}, i32 896
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+ ; CHECK-NEXT: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast ptr addrspace(1) %[[ATOMIC_ARG_1]] to ptr addrspace(4)
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+ ; CHECK-NEXT: call void @__itt_offload_atomic_op_finish(ptr addrspace(4) [[ARG_ASCAST]], i32 0, i32 0)
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+ %call3.i.i.i.i = tail call spir_func i32 @_Z18__spirv_AtomicLoadPU3AS1KiN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE (ptr addrspace (1 ) %add.ptr.i34 , i32 1 , i32 896 ) #2
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+ call spir_func void @__synthetic_spir_fun_call (ptr addrspace (1 ) %add.ptr.i34 )
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+ %ptridx.i.i.i = getelementptr inbounds i32 , ptr addrspace (1 ) %add.ptr.i , i64 %4
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+ %ptridx.ascast.i.i.i = addrspacecast ptr addrspace (1 ) %ptridx.i.i.i to ptr addrspace (4 )
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+ store i32 %call3.i.i.i.i , ptr addrspace (4 ) %ptridx.ascast.i.i.i , align 4 , !tbaa !14
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br label %_ZZN2cl4sycl7handler24parallel_for_lambda_implI11load_kernelIiEZZ9load_testIiEvNS0_5queueEmENKUlRS1_E_clES7_EUlNS0_4itemILi1ELb1EEEE_Li1EEEvNS0_5rangeIXT1_EEET0_ENKUlSA_E_clESA_.exit
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_ZZN2cl4sycl7handler24parallel_for_lambda_implI11load_kernelIiEZZ9load_testIiEvNS0_5queueEmENKUlRS1_E_clES7_EUlNS0_4itemILi1ELb1EEEE_Li1EEEvNS0_5rangeIXT1_EEET0_ENKUlSA_E_clESA_.exit: ; preds = %entry, %if.end.i
@@ -64,56 +64,56 @@ _ZZN2cl4sycl7handler24parallel_for_lambda_implI11load_kernelIiEZZ9load_testIiEvN
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ret void
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}
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- define weak_odr dso_local spir_func void @__synthetic_spir_fun_call (i32 addrspace (1 )* %ptr ) {
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+ define weak_odr dso_local spir_func void @__synthetic_spir_fun_call (ptr addrspace (1 ) %ptr ) {
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entry:
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- ; CHECK-LABEL: spir_func void @__synthetic_spir_fun_call(i32 addrspace(1)* %{{.*}} ) {
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+ ; CHECK-LABEL: spir_func void @__synthetic_spir_fun_call(ptr addrspace(1) %ptr ) {
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; CHECK-NEXT: entry:
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- ; CHECK-NEXT: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast i32 addrspace(1)* %[[ATOMIC_ARG_S:[0-9a-zA-Z._]+]] to i8 addrspace(4)*
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- ; CHECK-NEXT: call void @__itt_offload_atomic_op_start(i8 addrspace(4)* [[ARG_ASCAST]], i32 0, i32 0)
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- ; CHECK-NEXT: {{.*}}__spirv_AtomicLoad{{.*}}(i32 addrspace(1)* %[[ATOMIC_ARG_S]],{{.*}}, i32 896
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- ; CHECK-NEXT: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast i32 addrspace(1)* %[[ATOMIC_ARG_S]] to i8 addrspace(4)*
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- ; CHECK-NEXT: call void @__itt_offload_atomic_op_finish(i8 addrspace(4)* [[ARG_ASCAST]], i32 0, i32 0)
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- call spir_func i32 @_Z18__spirv_AtomicLoadPU3AS1KiN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE (i32 addrspace (1 )* %ptr , i32 1 , i32 896 ) #2
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+ ; CHECK-NEXT: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast ptr addrspace(1) %[[ATOMIC_ARG_S:[0-9a-zA-Z._]+]] to ptr addrspace(4)
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+ ; CHECK-NEXT: call void @__itt_offload_atomic_op_start(ptr addrspace(4) [[ARG_ASCAST]], i32 0, i32 0)
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+ ; CHECK-NEXT: {{.*}}__spirv_AtomicLoad{{.*}}(ptr addrspace(1) %[[ATOMIC_ARG_S]],{{.*}}, i32 896
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+ ; CHECK-NEXT: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast ptr addrspace(1) %[[ATOMIC_ARG_S]] to ptr addrspace(4)
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+ ; CHECK-NEXT: call void @__itt_offload_atomic_op_finish(ptr addrspace(4) [[ARG_ASCAST]], i32 0, i32 0)
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+ call spir_func i32 @_Z18__spirv_AtomicLoadPU3AS1KiN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE (ptr addrspace (1 ) %ptr , i32 1 , i32 896 ) #2
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; CHECK-NOT: call void @__itt_offload_wi_finish_wrapper()
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ret void
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}
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; Function Attrs: convergent
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- declare dso_local spir_func i32 @_Z18__spirv_AtomicLoadPU3AS1KiN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE (i32 addrspace (1 )* , i32 , i32 ) local_unnamed_addr #1
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+ declare dso_local spir_func i32 @_Z18__spirv_AtomicLoadPU3AS1KiN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE (ptr addrspace (1 ), i32 , i32 ) local_unnamed_addr #1
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; Function Attrs: convergent norecurse
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- define weak_odr dso_local spir_kernel void @_ZTS11load_kernelIiE (i32 addrspace (1 )* %_arg_ , % "class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" * byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_1 , % "class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" * byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_2 , % "class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" * byval (%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" ) align 8 %_arg_3 , i32 addrspace (1 )* %_arg_4 , % "class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" * byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_6 , % "class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" * byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_7 , % "class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" * byval (%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" ) align 8 %_arg_8 ) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !18 {
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+ define weak_odr dso_local spir_kernel void @_ZTS11load_kernelIiE (ptr addrspace (1 ) %_arg_ , ptr byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_1 , ptr byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_2 , ptr byval (%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" ) align 8 %_arg_3 , ptr addrspace (1 ) %_arg_4 , ptr byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_6 , ptr byval (%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" ) align 8 %_arg_7 , ptr byval (%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" ) align 8 %_arg_8 ) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !18 {
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entry:
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; CHECK-LABEL: _ZTS11load_kernelIiE(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: call void @__itt_offload_wi_start_wrapper()
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- %0 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" , % "class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" * %_arg_3 , i64 0 , i32 0 , i32 0 , i64 0
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- %1 = addrspacecast i64* %0 to i64 addrspace (4 )*
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- %2 = load i64 , i64 addrspace (4 )* %1 , align 8
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- %add.ptr.i32 = getelementptr inbounds i32 , i32 addrspace (1 )* %_arg_ , i64 %2
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- %3 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" , % "class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" * %_arg_8 , i64 0 , i32 0 , i32 0 , i64 0
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- %4 = addrspacecast i64* %3 to i64 addrspace (4 )*
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- %5 = load i64 , i64 addrspace (4 )* %4 , align 8
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- %add.ptr.i = getelementptr inbounds i32 , i32 addrspace (1 )* %_arg_4 , i64 %5
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- %6 = load <3 x i64 >, < 3 x i64 > addrspace (4 )* addrspacecast (< 3 x i64 > addrspace (1 )* @__spirv_BuiltInGlobalInvocationId to < 3 x i64 > addrspace (4 )* ), align 32 , !noalias !19
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+ %0 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" , ptr %_arg_3 , i64 0 , i32 0 , i32 0 , i64 0
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+ %1 = addrspacecast i64* %0 to ptr addrspace (4 )
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+ %2 = load i64 , ptr addrspace (4 ) %1 , align 8
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+ %add.ptr.i32 = getelementptr inbounds i32 , ptr addrspace (1 ) %_arg_ , i64 %2
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+ %3 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" , ptr %_arg_8 , i64 0 , i32 0 , i32 0 , i64 0
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+ %4 = addrspacecast i64* %3 to ptr addrspace (4 )
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+ %5 = load i64 , ptr addrspace (4 ) %4 , align 8
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+ %add.ptr.i = getelementptr inbounds i32 , ptr addrspace (1 ) %_arg_4 , i64 %5
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+ %6 = load <3 x i64 >, ptr addrspace (4 ) addrspacecast (ptr addrspace (1 ) @__spirv_BuiltInGlobalInvocationId to ptr addrspace (4 )), align 32 , !noalias !19
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%7 = extractelement <3 x i64 > %6 , i64 0
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- ; CHECK: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast i32 addrspace(1)* %[[ATOMIC_ARG_2:[0-9a-zA-Z._]+]] to i8 addrspace(4)*
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- ; CHECK-NEXT: call void @__itt_offload_atomic_op_start(i8 addrspace(4)* [[ARG_ASCAST]], i32 0, i32 0)
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- ; CHECK-NEXT: {{.*}}__spirv_AtomicLoad{{.*}}(i32 addrspace(1)* %[[ATOMIC_ARG_2]],{{.*}}, i32 896)
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- ; CHECK-NEXT: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast i32 addrspace(1)* %[[ATOMIC_ARG_2]] to i8 addrspace(4)*
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- ; CHECK-NEXT: call void @__itt_offload_atomic_op_finish(i8 addrspace(4)* [[ARG_ASCAST]], i32 0, i32 0)
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- %call3.i.i.i = tail call spir_func i32 @_Z18__spirv_AtomicLoadPU3AS1KiN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE (i32 addrspace (1 )* %add.ptr.i32 , i32 1 , i32 896 ) #2
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- %ptridx.i.i = getelementptr inbounds i32 , i32 addrspace (1 )* %add.ptr.i , i64 %7
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- %ptridx.ascast.i.i = addrspacecast i32 addrspace (1 )* %ptridx.i.i to i32 addrspace (4 )*
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- store i32 %call3.i.i.i , i32 addrspace (4 )* %ptridx.ascast.i.i , align 4 , !tbaa !14
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+ ; CHECK: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast ptr addrspace(1) %[[ATOMIC_ARG_2:[0-9a-zA-Z._]+]] to ptr addrspace(4)
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+ ; CHECK-NEXT: call void @__itt_offload_atomic_op_start(ptr addrspace(4) [[ARG_ASCAST]], i32 0, i32 0)
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+ ; CHECK-NEXT: {{.*}}__spirv_AtomicLoad{{.*}}(ptr addrspace(1) %[[ATOMIC_ARG_2]],{{.*}}, i32 896)
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+ ; CHECK-NEXT: [[ARG_ASCAST:%[0-9a-zA-Z._]+]] = addrspacecast ptr addrspace(1) %[[ATOMIC_ARG_2]] to ptr addrspace(4)
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+ ; CHECK-NEXT: call void @__itt_offload_atomic_op_finish(ptr addrspace(4) [[ARG_ASCAST]], i32 0, i32 0)
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+ %call3.i.i.i = tail call spir_func i32 @_Z18__spirv_AtomicLoadPU3AS1KiN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE (ptr addrspace (1 ) %add.ptr.i32 , i32 1 , i32 896 ) #2
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+ %ptridx.i.i = getelementptr inbounds i32 , ptr addrspace (1 ) %add.ptr.i , i64 %7
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+ %ptridx.ascast.i.i = addrspacecast ptr addrspace (1 ) %ptridx.i.i to ptr addrspace (4 )
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+ store i32 %call3.i.i.i , ptr addrspace (4 ) %ptridx.ascast.i.i , align 4 , !tbaa !14
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; CHECK: call void @__itt_offload_wi_finish_wrapper()
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; CHECK-NEXT: ret void
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ret void
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}
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; CHECK: declare void @__itt_offload_wi_start_wrapper()
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- ; CHECK: declare void @__itt_offload_atomic_op_start(i8 addrspace(4)* , i32, i32)
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- ; CHECK: declare void @__itt_offload_atomic_op_finish(i8 addrspace(4)* , i32, i32)
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+ ; CHECK: declare void @__itt_offload_atomic_op_start(ptr addrspace(4), i32, i32)
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+ ; CHECK: declare void @__itt_offload_atomic_op_finish(ptr addrspace(4), i32, i32)
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; CHECK: declare void @__itt_offload_wi_finish_wrapper()
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attributes #0 = { convergent norecurse "disable-tail-calls" ="false" "frame-pointer" ="all" "less-precise-fpmad" ="false" "min-legal-vector-width" ="0" "no-infs-fp-math" ="false" "no-jump-tables" ="false" "no-nans-fp-math" ="false" "no-signed-zeros-fp-math" ="false" "no-trapping-math" ="true" "stack-protector-buffer-size" ="8" "sycl-module-id" ="llvm-test-suite/SYCL/AtomicRef/load.cpp" "uniform-work-group-size" ="true" "unsafe-fp-math" ="false" "use-soft-float" ="false" }
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