Apply suggestions from code review

Co-authored-by: Alexey Bader <[email protected]>

Author: t4c1

libclc/ptx-nvidiacl/libspirv/atomic/atomic_helpers.h

@@ -72,4 +72,4 @@ Memory order is stored in the lowest 5 bits */
   __CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP,     \
                          NAME_MANGLED, __local, AS3, _shared_)
 
-#endif
+#endif

libclc/ptx-nvidiacl/libspirv/atomic/atomic_inc_dec_helpers.h

@@ -32,4 +32,4 @@
   __CLC_NVVM_ATOMIC_INCDEC_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, VAL, __local,  \
                                 AS3)
 
-#endif
+#endif

llvm/test/CodeGen/NVPTX/atomics-with-semantics.ll

@@ -2839,4 +2839,4 @@ declare i64 @llvm.nvvm.atomic.cas.gen.i.cta.acq.rel.i64.p0i64(i64* nocapture, i6
 declare i64 @llvm.nvvm.atomic.cas.global.i.cta.acq.rel.i64.p1i64(i64* nocapture, i64, i64) #1
 declare i64 @llvm.nvvm.atomic.cas.shared.i.cta.acq.rel.i64.p3i64(i64* nocapture, i64, i64) #1
 
-attributes #1 = { argmemonly nounwind }
+attributes #1 = { argmemonly nounwind }