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[llvm][SelectionDAGISel] support -{start|stop}-{before|after}= for remaining targets
Follow up to the series: 1. https://reviews.llvm.org/D140161 2. https://reviews.llvm.org/D140349 3. https://reviews.llvm.org/D140331 4. https://reviews.llvm.org/D140323 Completes the work from the previous two for remaining targets. This creates the following named passes that can be run via `llc -{start|stop}-{before|after}`: - arc-isel - arm-isel - avr-isel - bpf-isel - csky-isel - hexagon-isel - lanai-isel - loongarch-isel - m68k-isel - msp430-isel - mips-isel - nvptx-isel - ppc-codegen - riscv-isel - sparc-isel - systemz-isel - ve-isel - wasm-isel - xcore-isel A nice way to write tests for SelectionDAGISel might be to use a RUN: line like: llc -mtriple=<triple> -start-before=<arch>-isel -stop-after=finalize-isel -o - Fixes: llvm/llvm-project#59538 Reviewed By: asb, zixuan-wu Differential Revision: https://reviews.llvm.org/D140364
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‎llvm/lib/Target/ARC/ARC.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,14 +19,16 @@
1919

2020
namespace llvm {
2121

22-
class FunctionPass;
2322
class ARCTargetMachine;
23+
class FunctionPass;
24+
class PassRegistry;
2425

2526
FunctionPass *createARCISelDag(ARCTargetMachine &TM,
2627
CodeGenOpt::Level OptLevel);
2728
FunctionPass *createARCExpandPseudosPass();
2829
FunctionPass *createARCOptAddrMode();
2930
FunctionPass *createARCBranchFinalizePass();
31+
void initializeARCDAGToDAGISelPass(PassRegistry &);
3032

3133
} // end namespace llvm
3234

‎llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,9 @@
3232

3333
using namespace llvm;
3434

35+
#define DEBUG_TYPE "arc-isel"
36+
#define PASS_NAME "ARC DAG->DAG Pattern Instruction Selection"
37+
3538
/// ARCDAGToDAGISel - ARC specific code to select ARC machine
3639
/// instructions for SelectionDAG operations.
3740
namespace {
@@ -40,6 +43,8 @@ class ARCDAGToDAGISel : public SelectionDAGISel {
4043
public:
4144
static char ID;
4245

46+
ARCDAGToDAGISel() = delete;
47+
4348
ARCDAGToDAGISel(ARCTargetMachine &TM, CodeGenOpt::Level OptLevel)
4449
: SelectionDAGISel(ID, TM, OptLevel) {}
4550

@@ -51,16 +56,14 @@ class ARCDAGToDAGISel : public SelectionDAGISel {
5156
bool SelectAddrModeImm(SDValue Addr, SDValue &Base, SDValue &Offset);
5257
bool SelectAddrModeFar(SDValue Addr, SDValue &Base, SDValue &Offset);
5358

54-
StringRef getPassName() const override {
55-
return "ARC DAG->DAG Pattern Instruction Selection";
56-
}
57-
5859
// Include the pieces autogenerated from the target description.
5960
#include "ARCGenDAGISel.inc"
6061
};
6162

6263
char ARCDAGToDAGISel::ID;
6364

65+
INITIALIZE_PASS(ARCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
66+
6467
} // end anonymous namespace
6568

6669
/// This pass converts a legalized DAG into a ARC-specific DAG, ready for

‎llvm/lib/Target/ARC/ARCTargetMachine.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,8 @@ MachineFunctionInfo *ARCTargetMachine::createMachineFunctionInfo(
8989
// Force static initialization.
9090
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() {
9191
RegisterTargetMachine<ARCTargetMachine> X(getTheARCTarget());
92+
PassRegistry &PR = *PassRegistry::getPassRegistry();
93+
initializeARCDAGToDAGISelPass(PR);
9294
}
9395

9496
TargetTransformInfo

‎llvm/lib/Target/ARM/ARM.h

Lines changed: 13 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,8 @@ class ARMSubtarget;
2828
class Function;
2929
class FunctionPass;
3030
class InstructionSelector;
31-
class MachineInstr;
3231
class MCInst;
32+
class MachineInstr;
3333
class PassRegistry;
3434

3535
Pass *createMVETailPredicationPass();
@@ -62,23 +62,24 @@ FunctionPass *createARMFixCortexA57AES1742098Pass();
6262
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
6363
ARMAsmPrinter &AP);
6464

65-
void initializeARMParallelDSPPass(PassRegistry &);
66-
void initializeARMLoadStoreOptPass(PassRegistry &);
67-
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
65+
void initializeARMBlockPlacementPass(PassRegistry &);
6866
void initializeARMBranchTargetsPass(PassRegistry &);
6967
void initializeARMConstantIslandsPass(PassRegistry &);
68+
void initializeARMDAGToDAGISelPass(PassRegistry &);
7069
void initializeARMExpandPseudoPass(PassRegistry &);
71-
void initializeThumb2SizeReducePass(PassRegistry &);
72-
void initializeThumb2ITBlockPass(PassRegistry &);
73-
void initializeMVEVPTBlockPass(PassRegistry &);
74-
void initializeMVETPAndVPTOptimisationsPass(PassRegistry &);
70+
void initializeARMFixCortexA57AES1742098Pass(PassRegistry &);
71+
void initializeARMLoadStoreOptPass(PassRegistry &);
7572
void initializeARMLowOverheadLoopsPass(PassRegistry &);
76-
void initializeARMBlockPlacementPass(PassRegistry &);
77-
void initializeMVETailPredicationPass(PassRegistry &);
78-
void initializeMVEGatherScatterLoweringPass(PassRegistry &);
73+
void initializeARMParallelDSPPass(PassRegistry &);
74+
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
7975
void initializeARMSLSHardeningPass(PassRegistry &);
76+
void initializeMVEGatherScatterLoweringPass(PassRegistry &);
8077
void initializeMVELaneInterleavingPass(PassRegistry &);
81-
void initializeARMFixCortexA57AES1742098Pass(PassRegistry &);
78+
void initializeMVETPAndVPTOptimisationsPass(PassRegistry &);
79+
void initializeMVETailPredicationPass(PassRegistry &);
80+
void initializeMVEVPTBlockPass(PassRegistry &);
81+
void initializeThumb2ITBlockPass(PassRegistry &);
82+
void initializeThumb2SizeReducePass(PassRegistry &);
8283

8384
} // end namespace llvm
8485

‎llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@
4040
using namespace llvm;
4141

4242
#define DEBUG_TYPE "arm-isel"
43+
#define PASS_NAME "ARM Instruction Selection"
4344

4445
static cl::opt<bool>
4546
DisableShifterOp("disable-shifter-op", cl::Hidden,
@@ -60,6 +61,8 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
6061
public:
6162
static char ID;
6263

64+
ARMDAGToDAGISel() = delete;
65+
6366
explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel)
6467
: SelectionDAGISel(ID, tm, OptLevel) {}
6568

@@ -70,8 +73,6 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
7073
return true;
7174
}
7275

73-
StringRef getPassName() const override { return "ARM Instruction Selection"; }
74-
7576
void PreprocessISelDAG() override;
7677

7778
/// getI32Imm - Return a target constant of type i32 with the specified
@@ -364,6 +365,8 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
364365

365366
char ARMDAGToDAGISel::ID = 0;
366367

368+
INITIALIZE_PASS(ARMDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
369+
367370
/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
368371
/// operand. If so Imm will receive the 32-bit value.
369372
static bool isInt32Immediate(SDNode *N, unsigned &Imm) {

‎llvm/lib/Target/ARM/ARMTargetMachine.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
109109
initializeARMSLSHardeningPass(Registry);
110110
initializeMVELaneInterleavingPass(Registry);
111111
initializeARMFixCortexA57AES1742098Pass(Registry);
112+
initializeARMDAGToDAGISelPass(Registry);
112113
}
113114

114115
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {

‎llvm/lib/Target/AVR/AVR.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ namespace llvm {
2323

2424
class AVRTargetMachine;
2525
class FunctionPass;
26+
class PassRegistry;
2627

2728
Pass *createAVRShiftExpandPass();
2829
FunctionPass *createAVRISelDag(AVRTargetMachine &TM,
@@ -31,8 +32,9 @@ FunctionPass *createAVRExpandPseudoPass();
3132
FunctionPass *createAVRFrameAnalyzerPass();
3233
FunctionPass *createAVRBranchSelectionPass();
3334

34-
void initializeAVRShiftExpandPass(PassRegistry &);
35+
void initializeAVRDAGToDAGISelPass(PassRegistry &);
3536
void initializeAVRExpandPseudoPass(PassRegistry &);
37+
void initializeAVRShiftExpandPass(PassRegistry &);
3638

3739
/// Contains the AVR backend.
3840
namespace AVR {

‎llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -20,21 +20,22 @@
2020
#include "llvm/Support/raw_ostream.h"
2121

2222
#define DEBUG_TYPE "avr-isel"
23+
#define PASS_NAME "AVR DAG->DAG Instruction Selection"
2324

24-
namespace llvm {
25+
using namespace llvm;
26+
27+
namespace {
2528

2629
/// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form).
2730
class AVRDAGToDAGISel : public SelectionDAGISel {
2831
public:
2932
static char ID;
3033

34+
AVRDAGToDAGISel() = delete;
35+
3136
AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOpt::Level OptLevel)
3237
: SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
3338

34-
StringRef getPassName() const override {
35-
return "AVR DAG->DAG Instruction Selection";
36-
}
37-
3839
bool runOnMachineFunction(MachineFunction &MF) override;
3940

4041
bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
@@ -58,8 +59,12 @@ class AVRDAGToDAGISel : public SelectionDAGISel {
5859
const AVRSubtarget *Subtarget;
5960
};
6061

62+
} // namespace
63+
6164
char AVRDAGToDAGISel::ID = 0;
6265

66+
INITIALIZE_PASS(AVRDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
67+
6368
bool AVRDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
6469
Subtarget = &MF.getSubtarget<AVRSubtarget>();
6570
return SelectionDAGISel::runOnMachineFunction(MF);
@@ -579,10 +584,7 @@ bool AVRDAGToDAGISel::trySelect(SDNode *N) {
579584
}
580585
}
581586

582-
FunctionPass *createAVRISelDag(AVRTargetMachine &TM,
583-
CodeGenOpt::Level OptLevel) {
587+
FunctionPass *llvm::createAVRISelDag(AVRTargetMachine &TM,
588+
CodeGenOpt::Level OptLevel) {
584589
return new AVRDAGToDAGISel(TM, OptLevel);
585590
}
586-
587-
} // end of namespace llvm
588-

‎llvm/lib/Target/AVR/AVRTargetMachine.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTarget() {
9696
auto &PR = *PassRegistry::getPassRegistry();
9797
initializeAVRExpandPseudoPass(PR);
9898
initializeAVRShiftExpandPass(PR);
99+
initializeAVRDAGToDAGISelPass(PR);
99100
}
100101

101102
const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {

‎llvm/lib/Target/BPF/BPF.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,11 @@
1212
#include "MCTargetDesc/BPFMCTargetDesc.h"
1313
#include "llvm/IR/PassManager.h"
1414
#include "llvm/Pass.h"
15-
#include "llvm/PassRegistry.h"
1615
#include "llvm/Target/TargetMachine.h"
1716

1817
namespace llvm {
1918
class BPFTargetMachine;
19+
class PassRegistry;
2020

2121
ModulePass *createBPFAdjustOpt();
2222
ModulePass *createBPFCheckAndAdjustIR();
@@ -31,17 +31,17 @@ FunctionPass *createBPFMIPeepholeTruncElimPass();
3131
FunctionPass *createBPFMIPreEmitPeepholePass();
3232
FunctionPass *createBPFMIPreEmitCheckingPass();
3333

34+
void initializeBPFAbstractMemberAccessLegacyPassPass(PassRegistry &);
3435
void initializeBPFAdjustOptPass(PassRegistry&);
3536
void initializeBPFCheckAndAdjustIRPass(PassRegistry&);
36-
37-
void initializeBPFAbstractMemberAccessLegacyPassPass(PassRegistry &);
38-
void initializeBPFPreserveDITypePass(PassRegistry&);
39-
void initializeBPFIRPeepholePass(PassRegistry&);
40-
void initializeBPFMISimplifyPatchablePass(PassRegistry&);
37+
void initializeBPFDAGToDAGISelPass(PassRegistry &);
38+
void initializeBPFIRPeepholePass(PassRegistry &);
4139
void initializeBPFMIPeepholePass(PassRegistry&);
42-
void initializeBPFMIPeepholeTruncElimPass(PassRegistry&);
43-
void initializeBPFMIPreEmitPeepholePass(PassRegistry&);
40+
void initializeBPFMIPeepholeTruncElimPass(PassRegistry &);
4441
void initializeBPFMIPreEmitCheckingPass(PassRegistry&);
42+
void initializeBPFMIPreEmitPeepholePass(PassRegistry &);
43+
void initializeBPFMISimplifyPatchablePass(PassRegistry &);
44+
void initializeBPFPreserveDITypePass(PassRegistry &);
4545

4646
class BPFAbstractMemberAccessPass
4747
: public PassInfoMixin<BPFAbstractMemberAccessPass> {

‎llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434
using namespace llvm;
3535

3636
#define DEBUG_TYPE "bpf-isel"
37+
#define PASS_NAME "BPF DAG->DAG Pattern Instruction Selection"
3738

3839
// Instruction Selector Implementation
3940
namespace {
@@ -47,13 +48,11 @@ class BPFDAGToDAGISel : public SelectionDAGISel {
4748
public:
4849
static char ID;
4950

51+
BPFDAGToDAGISel() = delete;
52+
5053
explicit BPFDAGToDAGISel(BPFTargetMachine &TM)
5154
: SelectionDAGISel(ID, TM), Subtarget(nullptr) {}
5255

53-
StringRef getPassName() const override {
54-
return "BPF DAG->DAG Pattern Instruction Selection";
55-
}
56-
5756
bool runOnMachineFunction(MachineFunction &MF) override {
5857
// Reset the subtarget each time through.
5958
Subtarget = &MF.getSubtarget<BPFSubtarget>();
@@ -100,6 +99,8 @@ class BPFDAGToDAGISel : public SelectionDAGISel {
10099

101100
char BPFDAGToDAGISel::ID = 0;
102101

102+
INITIALIZE_PASS(BPFDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
103+
103104
// ComplexPattern used on BPF Load/Store instructions
104105
bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
105106
// if Address is FI, get the TargetFrameIndex.

‎llvm/lib/Target/BPF/BPFTargetMachine.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFTarget() {
4848
initializeBPFCheckAndAdjustIRPass(PR);
4949
initializeBPFMIPeepholePass(PR);
5050
initializeBPFMIPeepholeTruncElimPass(PR);
51+
initializeBPFDAGToDAGISelPass(PR);
5152
}
5253

5354
// DataLayout: little or big endian

‎llvm/lib/Target/CSKY/CSKY.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ FunctionPass *createCSKYISelDag(CSKYTargetMachine &TM,
2727
FunctionPass *createCSKYConstantIslandPass();
2828

2929
void initializeCSKYConstantIslandsPass(PassRegistry &);
30+
void initializeCSKYDAGToDAGISelPass(PassRegistry &);
3031

3132
} // namespace llvm
3233

‎llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
using namespace llvm;
2222

2323
#define DEBUG_TYPE "csky-isel"
24+
#define PASS_NAME "CSKY DAG->DAG Pattern Instruction Selection"
2425

2526
namespace {
2627
class CSKYDAGToDAGISel : public SelectionDAGISel {
@@ -32,10 +33,6 @@ class CSKYDAGToDAGISel : public SelectionDAGISel {
3233
explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM, CodeGenOpt::Level OptLevel)
3334
: SelectionDAGISel(ID, TM, OptLevel) {}
3435

35-
StringRef getPassName() const override {
36-
return "CSKY DAG->DAG Pattern Instruction Selection";
37-
}
38-
3936
bool runOnMachineFunction(MachineFunction &MF) override {
4037
// Reset the subtarget each time through.
4138
Subtarget = &MF.getSubtarget<CSKYSubtarget>();
@@ -60,6 +57,8 @@ class CSKYDAGToDAGISel : public SelectionDAGISel {
6057

6158
char CSKYDAGToDAGISel::ID = 0;
6259

60+
INITIALIZE_PASS(CSKYDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
61+
6362
void CSKYDAGToDAGISel::Select(SDNode *N) {
6463
// If we have a custom node, we have already selected
6564
if (N->isMachineOpcode()) {

‎llvm/lib/Target/CSKY/CSKYTargetMachine.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYTarget() {
2929

3030
PassRegistry *Registry = PassRegistry::getPassRegistry();
3131
initializeCSKYConstantIslandsPass(*Registry);
32+
initializeCSKYDAGToDAGISelPass(*Registry);
3233
}
3334

3435
static std::string computeDataLayout(const Triple &TT) {

‎llvm/lib/Target/Hexagon/Hexagon.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,12 @@
1717
namespace llvm {
1818
class HexagonTargetMachine;
1919
class ImmutablePass;
20+
class PassRegistry;
2021

2122
/// Creates a Hexagon-specific Target Transformation Info pass.
2223
ImmutablePass *createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM);
24+
25+
void initializeHexagonDAGToDAGISelPass(PassRegistry &);
2326
} // end namespace llvm;
2427

2528
#endif

‎llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@
2525
using namespace llvm;
2626

2727
#define DEBUG_TYPE "hexagon-isel"
28+
#define PASS_NAME "Hexagon DAG->DAG Pattern Instruction Selection"
2829

2930
static
3031
cl::opt<bool>
@@ -65,6 +66,8 @@ FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
6566

6667
char HexagonDAGToDAGISel::ID = 0;
6768

69+
INITIALIZE_PASS(HexagonDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
70+
6871
void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
6972
SDValue Chain = LD->getChain();
7073
SDValue Base = LD->getBasePtr();

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