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[SYCL] Add clang support for FPGA kernel attribute scheduler_target_fmax_mhz (#2511)
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‎clang/include/clang/Basic/Attr.td

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Original file line numberDiff line numberDiff line change
@@ -1225,6 +1225,24 @@ def SYCLIntelNumSimdWorkItems : InheritableAttr {
12251225
let PragmaAttributeSupport = 0;
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}
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1228+
def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
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let Spellings = [CXX11<"intelfpga","scheduler_target_fmax_mhz">];
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let Args = [ExprArgument<"Value">];
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let LangOpts = [SYCLIsDevice, SYCLIsHost];
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let Subjects = SubjectList<[Function], ErrorDiag>;
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let Documentation = [SYCLIntelSchedulerTargetFmaxMhzAttrDocs];
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let PragmaAttributeSupport = 0;
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let AdditionalMembers = [{
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static unsigned getMinValue() {
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return 0;
1238+
}
1239+
static unsigned getMaxValue() {
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return 1048576;
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}
1242+
}];
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}
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def SYCLIntelMaxWorkGroupSize : InheritableAttr {
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let Spellings = [CXX11<"intelfpga","max_work_group_size">];
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let Args = [UnsignedArgument<"XDim">,

‎clang/include/clang/Basic/AttrDocs.td

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2223,6 +2223,28 @@ device kernel, the attribute is ignored and it is not propagated to a kernel.
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}];
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}
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2226+
def SYCLIntelSchedulerTargetFmaxMhzAttrDocs : Documentation {
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let Category = DocCatFunction;
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let Heading = "scheduler_target_fmax_mhz (IntelFPGA)";
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let Content = [{
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Applies to a device function/lambda function. Indicates that the kernel should
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be pipelined so as to achieve the specified target clock frequency (Fmax) of N
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MHz. The argument N may be a template parameter. This attribute should be
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ignored for the FPGA emulator device.
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``[[intelfpga::scheduler_target_fmax_mhz(N)]]``
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Valid values of N are integers in the range [0, 1048576]. The upper limit,
2237+
although too high to be a realistic value for frequency, is chosen to be future
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proof. The FPGA backend emits a diagnostic message if the passed value is
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unachievable by the device.
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This attribute enables communication of the desired maximum frequency of the
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device operation, guiding the FPGA backend to insert the appropriate number of
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registers to break-up the combinational logic circuit, and thereby controlling
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the length of the longest combinational path.
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}];
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}
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def SYCLIntelNoGlobalWorkOffsetAttrDocs : Documentation {
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let Category = DocCatFunction;
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let Heading = "no_global_work_offset (IntelFPGA)";

‎clang/include/clang/Basic/AttributeCommonInfo.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -162,6 +162,7 @@ class AttributeCommonInfo {
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(ParsedAttr == AT_ReqdWorkGroupSize && isCXX11Attribute()) ||
163163
(ParsedAttr == AT_IntelReqdSubGroupSize && isCXX11Attribute()) ||
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ParsedAttr == AT_SYCLIntelNumSimdWorkItems ||
165+
ParsedAttr == AT_SYCLIntelSchedulerTargetFmaxMhz ||
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ParsedAttr == AT_SYCLIntelMaxWorkGroupSize ||
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ParsedAttr == AT_SYCLIntelMaxGlobalWorkDim ||
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ParsedAttr == AT_SYCLIntelNoGlobalWorkOffset)

‎clang/include/clang/Sema/Sema.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10060,6 +10060,11 @@ class Sema final {
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bool checkAllowedSYCLInitializer(VarDecl *VD,
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bool CheckValueDependent = false);
1006210062

10063+
// Adds a scheduler_target_fmax_mhz attribute to a particular declaration.
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void addSYCLIntelSchedulerTargetFmaxMhzAttr(Decl *D,
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const AttributeCommonInfo &CI,
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Expr *E);
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//===--------------------------------------------------------------------===//
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// C++ Coroutines TS
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//

‎clang/lib/CodeGen/CodeGenFunction.cpp

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Original file line numberDiff line numberDiff line change
@@ -641,6 +641,17 @@ void CodeGenFunction::EmitOpenCLKernelMetadata(const FunctionDecl *FD,
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llvm::MDNode::get(Context, AttrMDArgs));
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}
643643

644+
if (const SYCLIntelSchedulerTargetFmaxMhzAttr *A =
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FD->getAttr<SYCLIntelSchedulerTargetFmaxMhzAttr>()) {
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Optional<llvm::APSInt> ArgVal =
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A->getValue()->getIntegerConstantExpr(FD->getASTContext());
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assert(ArgVal.hasValue() && "Not an integer constant expression");
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llvm::Metadata *AttrMDArgs[] = {llvm::ConstantAsMetadata::get(
650+
Builder.getInt32(ArgVal->getSExtValue()))};
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Fn->setMetadata("scheduler_target_fmax_mhz",
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llvm::MDNode::get(Context, AttrMDArgs));
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}
654+
644655
if (const SYCLIntelMaxWorkGroupSizeAttr *A =
645656
FD->getAttr<SYCLIntelMaxWorkGroupSizeAttr>()) {
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llvm::Metadata *AttrMDArgs[] = {

‎clang/lib/Sema/SemaDeclAttr.cpp

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3006,6 +3006,38 @@ static void handleNumSimdWorkItemsAttr(Sema &S, Decl *D,
30063006
E);
30073007
}
30083008

3009+
// Add scheduler_target_fmax_mhz
3010+
void Sema::addSYCLIntelSchedulerTargetFmaxMhzAttr(
3011+
Decl *D, const AttributeCommonInfo &Attr, Expr *E) {
3012+
assert(E && "Attribute must have an argument.");
3013+
3014+
SYCLIntelSchedulerTargetFmaxMhzAttr TmpAttr(Context, Attr, E);
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if (!E->isValueDependent()) {
3016+
ExprResult ResultExpr;
3017+
if (checkRangedIntegralArgument<SYCLIntelSchedulerTargetFmaxMhzAttr>(
3018+
E, &TmpAttr, ResultExpr))
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return;
3020+
E = ResultExpr.get();
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}
3022+
3023+
D->addAttr(::new (Context)
3024+
SYCLIntelSchedulerTargetFmaxMhzAttr(Context, Attr, E));
3025+
}
3026+
3027+
// Handle scheduler_target_fmax_mhz
3028+
static void handleSchedulerTargetFmaxMhzAttr(Sema &S, Decl *D,
3029+
const ParsedAttr &AL) {
3030+
if (D->isInvalidDecl())
3031+
return;
3032+
3033+
Expr *E = AL.getArgAsExpr(0);
3034+
3035+
if (D->getAttr<SYCLIntelSchedulerTargetFmaxMhzAttr>())
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S.Diag(AL.getLoc(), diag::warn_duplicate_attribute) << AL;
3037+
3038+
S.addSYCLIntelSchedulerTargetFmaxMhzAttr(D, AL, E);
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}
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// Handles max_global_work_dim.
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static void handleMaxGlobalWorkDimAttr(Sema &S, Decl *D,
30113043
const ParsedAttr &Attr) {
@@ -8225,6 +8257,9 @@ static void ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D,
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case ParsedAttr::AT_SYCLIntelNumSimdWorkItems:
82268258
handleNumSimdWorkItemsAttr(S, D, AL);
82278259
break;
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case ParsedAttr::AT_SYCLIntelSchedulerTargetFmaxMhz:
8261+
handleSchedulerTargetFmaxMhzAttr(S, D, AL);
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break;
82288263
case ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim:
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handleMaxGlobalWorkDimAttr(S, D, AL);
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break;

‎clang/lib/Sema/SemaSYCL.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -531,6 +531,9 @@ class MarkDeviceFunction : public RecursiveASTVisitor<MarkDeviceFunction> {
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if (auto *A = FD->getAttr<SYCLIntelNumSimdWorkItemsAttr>())
532532
Attrs.insert(A);
533533

534+
if (auto *A = FD->getAttr<SYCLIntelSchedulerTargetFmaxMhzAttr>())
535+
Attrs.insert(A);
536+
534537
if (auto *A = FD->getAttr<SYCLIntelMaxWorkGroupSizeAttr>())
535538
Attrs.insert(A);
536539

@@ -3166,6 +3169,7 @@ void Sema::MarkDevice(void) {
31663169
}
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case attr::Kind::SYCLIntelKernelArgsRestrict:
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case attr::Kind::SYCLIntelNumSimdWorkItems:
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case attr::Kind::SYCLIntelSchedulerTargetFmaxMhz:
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case attr::Kind::SYCLIntelMaxGlobalWorkDim:
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case attr::Kind::SYCLIntelNoGlobalWorkOffset:
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case attr::Kind::SYCLSimd: {

‎clang/lib/Sema/SemaTemplateInstantiateDecl.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -737,6 +737,12 @@ void Sema::InstantiateAttrs(const MultiLevelTemplateArgumentList &TemplateArgs,
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*this, TemplateArgs, SYCLIntelNumSimdWorkItems, New);
738738
continue;
739739
}
740+
if (const auto *SYCLIntelSchedulerTargetFmaxMhz =
741+
dyn_cast<SYCLIntelSchedulerTargetFmaxMhzAttr>(TmplAttr)) {
742+
instantiateIntelSYCLFunctionAttr<SYCLIntelSchedulerTargetFmaxMhzAttr>(
743+
*this, TemplateArgs, SYCLIntelSchedulerTargetFmaxMhz, New);
744+
continue;
745+
}
740746
// Existing DLL attribute on the instantiation takes precedence.
741747
if (TmplAttr->getKind() == attr::DLLExport ||
742748
TmplAttr->getKind() == attr::DLLImport) {

‎clang/test/CodeGenSYCL/scheduler-target-fmax-mhz.cpp

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
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// RUN: %clang_cc1 -fsycl -fsycl-is-device -disable-llvm-passes -triple spir64-unknown-unknown-sycldevice -emit-llvm -o - %s | FileCheck %s
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#include "Inputs/sycl.hpp"
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[[intelfpga::scheduler_target_fmax_mhz(5)]] void
5+
func() {}
6+
7+
template <int N>
8+
[[intelfpga::scheduler_target_fmax_mhz(N)]] void zoo() {}
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int main() {
11+
cl::sycl::kernel_single_task<class test_kernel1>(
12+
[]() [[intelfpga::scheduler_target_fmax_mhz(2)]]{});
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cl::sycl::kernel_single_task<class test_kernel2>(
15+
[]() { func(); });
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cl::sycl::kernel_single_task<class test_kernel3>(
18+
[]() { zoo<75>(); });
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}
20+
// CHECK: define spir_kernel void @{{.*}}test_kernel1() {{.*}} !scheduler_target_fmax_mhz ![[PARAM1:[0-9]+]]
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// CHECK: define spir_kernel void @{{.*}}test_kernel2() {{.*}} !scheduler_target_fmax_mhz ![[PARAM2:[0-9]+]]
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// CHECK: define spir_kernel void @{{.*}}test_kernel3() {{.*}} !scheduler_target_fmax_mhz ![[PARAM3:[0-9]+]]
23+
// CHECK: ![[PARAM1]] = !{i32 2}
24+
// CHECK: ![[PARAM2]] = !{i32 5}
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// CHECK: ![[PARAM3]] = !{i32 75}

‎clang/test/SemaSYCL/scheduler_target_fmax_mhz.cpp

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
// RUN: %clang_cc1 %s -fsyntax-only -ast-dump -fsycl -fsycl-is-device -triple spir64 -Wno-sycl-2017-compat -verify | FileCheck %s
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3+
#include "Inputs/sycl.hpp"
4+
[[intelfpga::scheduler_target_fmax_mhz(2)]] void
5+
func() {}
6+
7+
template <int N>
8+
[[intelfpga::scheduler_target_fmax_mhz(N)]] void zoo() {}
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10+
int main() {
11+
// CHECK-LABEL: FunctionDecl {{.*}}test_kernel1 'void ()'
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// CHECK: SYCLIntelSchedulerTargetFmaxMhzAttr {{.*}}
13+
// CHECK-NEXT: ConstantExpr {{.*}} 'int'
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// CHECK-NEXT: value: Int 5
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 5
16+
cl::sycl::kernel_single_task<class test_kernel1>(
17+
[]() [[intelfpga::scheduler_target_fmax_mhz(5)]]{});
18+
19+
// CHECK-LABEL: FunctionDecl {{.*}}test_kernel2 'void ()'
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// CHECK: SYCLIntelSchedulerTargetFmaxMhzAttr {{.*}}
21+
// CHECK-NEXT: ConstantExpr {{.*}} 'int'
22+
// CHECK-NEXT: value: Int 2
23+
// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 2
24+
cl::sycl::kernel_single_task<class test_kernel2>(
25+
[]() { func(); });
26+
27+
// CHECK-LABEL: FunctionDecl {{.*}}test_kernel3 'void ()'
28+
// CHECK: SYCLIntelSchedulerTargetFmaxMhzAttr {{.*}}
29+
// CHECK-NEXT: SubstNonTypeTemplateParmExpr {{.*}} 'int'
30+
// CHECK-NEXT: NonTypeTemplateParmDecl {{.*}} referenced 'int' depth 0 index 0 N
31+
// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 75
32+
cl::sycl::kernel_single_task<class test_kernel3>(
33+
[]() { zoo<75>(); });
34+
35+
[[intelfpga::scheduler_target_fmax_mhz(0)]] int Var = 0; // expected-error{{'scheduler_target_fmax_mhz' attribute only applies to functions}}
36+
37+
cl::sycl::kernel_single_task<class test_kernel4>(
38+
[]() [[intelfpga::scheduler_target_fmax_mhz(1048577)]]{}); // expected-error{{'scheduler_target_fmax_mhz' attribute requires integer constant between 0 and 1048576 inclusive}}
39+
40+
cl::sycl::kernel_single_task<class test_kernel5>(
41+
[]() [[intelfpga::scheduler_target_fmax_mhz(-4)]]{}); // expected-error{{'scheduler_target_fmax_mhz' attribute requires integer constant between 0 and 1048576 inclusive}}
42+
43+
cl::sycl::kernel_single_task<class test_kernel6>(
44+
[]() [[intelfpga::scheduler_target_fmax_mhz(1), intelfpga::scheduler_target_fmax_mhz(2)]]{}); // expected-warning{{attribute 'scheduler_target_fmax_mhz' is already applied with different parameters}}
45+
}

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