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Update tests after LLVM IR splat syntax change (#2829)
Update for LLVM commit 38fffa6 ("[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)", 2024-11-06). Original commit: KhronosGroup/SPIRV-LLVM-Translator@cf697333b60d200
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‎llvm-spirv/test/ExtendBitBoolArg.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@
1616
; CHECK: %[[#LSHR:]] = lshr i32 %[[#ExtBase]], %[[#ExtShift]]
1717
; CHECK: and i32 %[[#LSHR]], 1
1818

19-
; CHECK: %[[#ExtVecBase:]] = select <2 x i1> %vec1, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
20-
; CHECK: %[[#ExtVecShift:]] = select <2 x i1> %vec2, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
19+
; CHECK: %[[#ExtVecBase:]] = select <2 x i1> %vec1, <2 x i32> splat (i32 1), <2 x i32> zeroinitializer
20+
; CHECK: %[[#ExtVecShift:]] = select <2 x i1> %vec2, <2 x i32> splat (i32 1), <2 x i32> zeroinitializer
2121
; CHECK: lshr <2 x i32> %[[#ExtVecBase]], %[[#ExtVecShift]]
2222

2323
; ModuleID = 'source.bc'

‎llvm-spirv/test/SpecConstants/specconstantop-init.spvasm

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@
3232
; CHECK: @var_bitand = addrspace(1) global i32 52
3333
; CHECK: @var_vecshuf = addrspace(1) global <2 x i32> <i32 4, i32 53>
3434
; CHECK: @var_compext = addrspace(1) global i32 53
35-
; CHECK: @var_compins = addrspace(1) global <2 x i32> <i32 53, i32 53>
35+
; CHECK: @var_compins = addrspace(1) global <2 x i32> splat (i32 53)
3636
; CHECK: @var_logor = addrspace(1) global i1 true
3737
; CHECK: @var_logand = addrspace(1) global i1 false
3838
; CHECK: @var_lognot = addrspace(1) global i1 false

‎llvm-spirv/test/complex-constexpr-vector.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -44,14 +44,14 @@ entry:
4444
; CHECK-LLVM: #dbg_value(
4545
; CHECK-LLVM-SAME: <4 x i8> <
4646
; CHECK-LLVM-SAME: i8 add (
47-
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> <i32 65793, i32 65793> to <8 x i8>), i32 0),
48-
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> <i32 131586, i32 131586> to <8 x i8>), i32 0)),
47+
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> splat (i32 65793) to <8 x i8>), i32 0),
48+
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> splat (i32 131586) to <8 x i8>), i32 0)),
4949
; CHECK-LLVM-SAME: i8 add (
50-
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> <i32 65793, i32 65793> to <8 x i8>), i32 1),
51-
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> <i32 131586, i32 131586> to <8 x i8>), i32 1)),
50+
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> splat (i32 65793) to <8 x i8>), i32 1),
51+
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> splat (i32 131586) to <8 x i8>), i32 1)),
5252
; CHECK-LLVM-SAME: i8 add (
53-
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> <i32 65793, i32 65793> to <8 x i8>), i32 2),
54-
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> <i32 131586, i32 131586> to <8 x i8>), i32 2)),
53+
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> splat (i32 65793) to <8 x i8>), i32 2),
54+
; CHECK-LLVM-SAME: i8 extractelement (<8 x i8> bitcast (<2 x i32> splat (i32 131586) to <8 x i8>), i32 2)),
5555
; CHECK-LLVM-SAME: i8 undef>,
5656
; CHECK-LLVM-SAME: ![[#]], !DIExpression(), ![[#]])
5757
call void @llvm.dbg.value(

‎llvm-spirv/test/extensions/INTEL/SPV_INTEL_masked_gather_scatter/intel-gather-scatter.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@
4343
; CHECK-LLVM: %[[#VECGATHER:]] = load <4 x ptr addrspace(4)>, ptr
4444
; CHECK-LLVM: %[[#VECSCATTER:]] = load <4 x ptr addrspace(4)>, ptr
4545
; CHECK-LLVM: %[[GATHER:[a-z0-9]+]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)> %[[#VECGATHER]], i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> <i32 4, i32 0, i32 1, i32 0>)
46-
; CHECK-LLVM: call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %[[GATHER]], <4 x ptr addrspace(4)> %[[#VECSCATTER]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
46+
; CHECK-LLVM: call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %[[GATHER]], <4 x ptr addrspace(4)> %[[#VECSCATTER]], i32 4, <4 x i1> splat (i1 true))
4747

4848
; CHECK-LLVM-DAG: declare <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)>, i32 immarg, <4 x i1>, <4 x i32>)
4949
; CHECK-LLVM-DAG: declare void @llvm.masked.scatter.v4i32.v4p4(<4 x i32>, <4 x ptr addrspace(4)>, i32 immarg, <4 x i1>)
@@ -59,7 +59,7 @@ entry:
5959
%0 = load <4 x ptr addrspace(4)>, ptr %arg0
6060
%1 = load <4 x ptr addrspace(4)>, ptr %arg1
6161
%res = call <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)> %0, i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> <i32 4, i32 0, i32 1, i32 0>)
62-
call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %res, <4 x ptr addrspace(4)> %1, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
62+
call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %res, <4 x ptr addrspace(4)> %1, i32 4, <4 x i1> splat (i1 true))
6363
ret void
6464
}
6565

‎llvm-spirv/test/lshr_shl_i1_regularize.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,8 +43,8 @@ entry:
4343
define spir_func void @test_shl_vec_i1(<8 x i1> %a, <8 x i1> %b) {
4444
entry:
4545
%0 = shl <8 x i1> %a, %b
46-
; CHECK-LLVM: [[AI32_2:%[0-9]+]] = select <8 x i1> %a, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <8 x i32> zeroinitializer
47-
; CHECK-LLVM: [[BI32_2:%[0-9]+]] = select <8 x i1> %b, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <8 x i32> zeroinitializer
46+
; CHECK-LLVM: [[AI32_2:%[0-9]+]] = select <8 x i1> %a, <8 x i32> splat (i32 1), <8 x i32> zeroinitializer
47+
; CHECK-LLVM: [[BI32_2:%[0-9]+]] = select <8 x i1> %b, <8 x i32> splat (i32 1), <8 x i32> zeroinitializer
4848
; CHECK-LLVM: [[LSHR32_2:%[0-9]+]] = lshr <8 x i32> [[AI32_2]], [[BI32_2]]
4949
; CHECK-LLVM: [[TRUNC_2:%[0-9]+]] = icmp ne <8 x i32> [[LSHR32_2]], zeroinitializer
5050
%1 = zext <8 x i1> %0 to <8 x i32>

‎llvm-spirv/test/transcoding/relationals_select.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -75,31 +75,31 @@ entry:
7575
; CHECK: [[DATA10:%.*]] = call spir_func <4 x i32> @_Z8isnormalDv4_f(<4 x float> [[ARG1:%.*]]) #0
7676
; CHECK-NEXT: [[DATA11:%.*]] = trunc <4 x i32> [[DATA10]] to <4 x i8>
7777
; CHECK-NEXT: [[DATA12:%.*]] = trunc <4 x i8> [[DATA11]] to <4 x i1>
78-
; CHECK-NEXT: [[CALL5:%.*]] = select <4 x i1> [[DATA12]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer
78+
; CHECK-NEXT: [[CALL5:%.*]] = select <4 x i1> [[DATA12]], <4 x i32> splat (i32 -1), <4 x i32> zeroinitializer
7979
%call7 = tail call spir_func <4 x i32> @_Z8isnormalDv4_f(<4 x float> noundef %v) #2
8080

8181
; CHECK: [[DATA13:%.*]] = call spir_func <4 x i32> @_Z8isfiniteDv4_f(<4 x float> [[ARG1]]) #0
8282
; CHECK-NEXT: [[DATA14:%.*]] = trunc <4 x i32> [[DATA13]] to <4 x i8>
8383
; CHECK-NEXT: [[DATA15:%.*]] = trunc <4 x i8> [[DATA14]] to <4 x i1>
84-
; CHECK-NEXT: [[CALL6:%.*]] = select <4 x i1> [[DATA15]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer
84+
; CHECK-NEXT: [[CALL6:%.*]] = select <4 x i1> [[DATA15]], <4 x i32> splat (i32 -1), <4 x i32> zeroinitializer
8585
%call8 = tail call spir_func <4 x i32> @_Z8isfiniteDv4_f(<4 x float> noundef %v) #2
8686

8787
; CHECK: [[DATA16:%.*]] = call spir_func <4 x i32> @_Z5isnanDv4_f(<4 x float> [[ARG1]]) #0
8888
; CHECK-NEXT: [[DATA17:%.*]] = trunc <4 x i32> [[DATA16]] to <4 x i8>
8989
; CHECK-NEXT: [[DATA18:%.*]] = trunc <4 x i8> [[DATA17]] to <4 x i1>
90-
; CHECK-NEXT: [[CALL7:%.*]] = select <4 x i1> [[DATA18]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer
90+
; CHECK-NEXT: [[CALL7:%.*]] = select <4 x i1> [[DATA18]], <4 x i32> splat (i32 -1), <4 x i32> zeroinitializer
9191
%call9 = tail call spir_func <4 x i32> @_Z5isnanDv4_f(<4 x float> noundef %v) #2
9292

9393
; CHECK: [[DATA19:%.*]] = call spir_func <4 x i32> @_Z5isinfDv4_f(<4 x float> [[ARG1]]) #0
9494
; CHECK-NEXT: [[DATA20:%.*]] = trunc <4 x i32> [[DATA19]] to <4 x i8>
9595
; CHECK-NEXT: [[DATA21:%.*]] = trunc <4 x i8> [[DATA20]] to <4 x i1>
96-
; CHECK-NEXT: [[CALL8:%.*]] = select <4 x i1> [[DATA21]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer
96+
; CHECK-NEXT: [[CALL8:%.*]] = select <4 x i1> [[DATA21]], <4 x i32> splat (i32 -1), <4 x i32> zeroinitializer
9797
%call10 = tail call spir_func <4 x i32> @_Z5isinfDv4_f(<4 x float> noundef %v) #2
9898

9999
; CHECK: [[DATA22:%.*]] = call spir_func <4 x i32> @_Z7signbitDv4_f(<4 x float> [[ARG1]]) #0
100100
; CHECK-NEXT: [[DATA23:%.*]] = trunc <4 x i32> [[DATA22]] to <4 x i8>
101101
; CHECK-NEXT: [[DATA24:%.*]] = trunc <4 x i8> [[DATA23]] to <4 x i1>
102-
; CHECK-NEXT: [[CALL9:%.*]] = select <4 x i1> [[DATA24]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer
102+
; CHECK-NEXT: [[CALL9:%.*]] = select <4 x i1> [[DATA24]], <4 x i32> splat (i32 -1), <4 x i32> zeroinitializer
103103
%call11 = tail call spir_func <4 x i32> @_Z7signbitDv4_f(<4 x float> noundef %v) #2
104104
ret void
105105
}

‎llvm-spirv/test/uitofp-with-bool.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -114,16 +114,16 @@ entry:
114114
; LLVM-DAG: %s4 = select i1 %i1s, i64 -1, i64 0
115115
%s4 = sext i1 %i1s to i64
116116
; SPV-DAG: Select [[vec_8]] [[s5]] [[i1v]] [[mones_8]] [[zeros_8]]
117-
; LLVM-DAG: %s5 = select <2 x i1> %i1v, <2 x i8> <i8 -1, i8 -1>, <2 x i8> zeroinitializer
117+
; LLVM-DAG: %s5 = select <2 x i1> %i1v, <2 x i8> splat (i8 -1), <2 x i8> zeroinitializer
118118
%s5 = sext <2 x i1> %i1v to <2 x i8>
119119
; SPV-DAG: Select [[vec_16]] [[s6]] [[i1v]] [[mones_16]] [[zeros_16]]
120-
; LLVM-DAG: %s6 = select <2 x i1> %i1v, <2 x i16> <i16 -1, i16 -1>, <2 x i16> zeroinitializer
120+
; LLVM-DAG: %s6 = select <2 x i1> %i1v, <2 x i16> splat (i16 -1), <2 x i16> zeroinitializer
121121
%s6 = sext <2 x i1> %i1v to <2 x i16>
122122
; SPV-DAG: Select [[vec_32]] [[s7]] [[i1v]] [[mones_32]] [[zeros_32]]
123-
; LLVM-DAG: %s7 = select <2 x i1> %i1v, <2 x i32> <i32 -1, i32 -1>, <2 x i32> zeroinitializer
123+
; LLVM-DAG: %s7 = select <2 x i1> %i1v, <2 x i32> splat (i32 -1), <2 x i32> zeroinitializer
124124
%s7 = sext <2 x i1> %i1v to <2 x i32>
125125
; SPV-DAG: Select [[vec_64]] [[s8]] [[i1v]] [[mones_64]] [[zeros_64]]
126-
; LLVM-DAG: %s8 = select <2 x i1> %i1v, <2 x i64> <i64 -1, i64 -1>, <2 x i64> zeroinitializer
126+
; LLVM-DAG: %s8 = select <2 x i1> %i1v, <2 x i64> splat (i64 -1), <2 x i64> zeroinitializer
127127
%s8 = sext <2 x i1> %i1v to <2 x i64>
128128
; SPV-DAG: Select [[int_8]] [[z1]] [[i1s]] [[one_8]] [[zero_8]]
129129
; LLVM-DAG: %z1 = select i1 %i1s, i8 1, i8 0
@@ -138,16 +138,16 @@ entry:
138138
; LLVM-DAG: %z4 = select i1 %i1s, i64 1, i64 0
139139
%z4 = zext i1 %i1s to i64
140140
; SPV-DAG: Select [[vec_8]] [[z5]] [[i1v]] [[ones_8]] [[zeros_8]]
141-
; LLVM-DAG: %z5 = select <2 x i1> %i1v, <2 x i8> <i8 1, i8 1>, <2 x i8> zeroinitializer
141+
; LLVM-DAG: %z5 = select <2 x i1> %i1v, <2 x i8> splat (i8 1), <2 x i8> zeroinitializer
142142
%z5 = zext <2 x i1> %i1v to <2 x i8>
143143
; SPV-DAG: Select [[vec_16]] [[z6]] [[i1v]] [[ones_16]] [[zeros_16]]
144-
; LLVM-DAG: %z6 = select <2 x i1> %i1v, <2 x i16> <i16 1, i16 1>, <2 x i16> zeroinitializer
144+
; LLVM-DAG: %z6 = select <2 x i1> %i1v, <2 x i16> splat (i16 1), <2 x i16> zeroinitializer
145145
%z6 = zext <2 x i1> %i1v to <2 x i16>
146146
; SPV-DAG: Select [[vec_32]] [[z7]] [[i1v]] [[ones_32]] [[zeros_32]]
147-
; LLVM-DAG: %z7 = select <2 x i1> %i1v, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
147+
; LLVM-DAG: %z7 = select <2 x i1> %i1v, <2 x i32> splat (i32 1), <2 x i32> zeroinitializer
148148
%z7 = zext <2 x i1> %i1v to <2 x i32>
149149
; SPV-DAG: Select [[vec_64]] [[z8]] [[i1v]] [[ones_64]] [[zeros_64]]
150-
; LLVM-DAG: %z8 = select <2 x i1> %i1v, <2 x i64> <i64 1, i64 1>, <2 x i64> zeroinitializer
150+
; LLVM-DAG: %z8 = select <2 x i1> %i1v, <2 x i64> splat (i64 1), <2 x i64> zeroinitializer
151151
%z8 = zext <2 x i1> %i1v to <2 x i64>
152152
; SPV-DAG: Select [[int_32]] [[ufp1_res:[0-9]+]] [[i1s]] [[one_32]] [[zero_32]]
153153
; SPV-DAG: ConvertUToF [[float]] [[ufp1]] [[ufp1_res]]
@@ -156,7 +156,7 @@ entry:
156156
%ufp1 = uitofp i1 %i1s to float
157157
; SPV-DAG: Select [[vec_32]] [[ufp2_res:[0-9]+]] [[i1v]] [[ones_32]] [[zeros_32]]
158158
; SPV-DAG: ConvertUToF [[vec_float]] [[ufp2]] [[ufp2_res]]
159-
; LLVM-DAG: %[[ufp2_res_llvm:[0-9]+]] = select <2 x i1> %i1v, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
159+
; LLVM-DAG: %[[ufp2_res_llvm:[0-9]+]] = select <2 x i1> %i1v, <2 x i32> splat (i32 1), <2 x i32> zeroinitializer
160160
; LLVM-DAG: %ufp2 = uitofp <2 x i32> %[[ufp2_res_llvm]] to <2 x float>
161161
%ufp2 = uitofp <2 x i1> %i1v to <2 x float>
162162
; SPV-DAG: Select [[int_32]] [[sfp1_res:[0-9]+]] [[i1s]] [[one_32]] [[zero_32]]
@@ -166,7 +166,7 @@ entry:
166166
%sfp1 = sitofp i1 %i1s to float
167167
; SPV-DAG: Select [[vec_32]] [[sfp2_res:[0-9]+]] [[i1v]] [[ones_32]] [[zeros_32]]
168168
; SPV-DAG: ConvertSToF [[vec_float]] [[sfp2]] [[sfp2_res]]
169-
; LLVM-DAG: %[[sfp2_res_llvm:[0-9]+]] = select <2 x i1> %i1v, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
169+
; LLVM-DAG: %[[sfp2_res_llvm:[0-9]+]] = select <2 x i1> %i1v, <2 x i32> splat (i32 1), <2 x i32> zeroinitializer
170170
; LLVM-DAG: %sfp2 = sitofp <2 x i32> %[[sfp2_res_llvm]] to <2 x float>
171171
%sfp2 = sitofp <2 x i1> %i1v to <2 x float>
172172
ret void

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