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[ESIMD][NFC] Add function extracting L1/L2 hint for esimd/genx intrin (#13275)
Signed-off-by: Klochkov, Vyacheslav N <[email protected]> Co-authored-by: Nick Sarnie <[email protected]>
1 parent 13b72b3 commit 239f1aa

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+67
-97
lines changed

2 files changed

+67
-97
lines changed

‎sycl/include/sycl/ext/intel/esimd/common.hpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -545,7 +545,8 @@ template <cache_hint Hint> class cache_hint_wrap {
545545
}
546546
};
547547

548-
constexpr bool are_both(cache_hint First, cache_hint Second, cache_hint Val) {
548+
template <cache_hint Val>
549+
constexpr bool are_all(cache_hint First, cache_hint Second) {
549550
return First == Val && Second == Val;
550551
}
551552

@@ -559,9 +560,8 @@ template <typename PropertyListT> constexpr bool has_cache_hints() {
559560
return L1H != cache_hint::none || L2H != cache_hint::none;
560561
}
561562

562-
// Currently, this is just a wrapper around 'check_cache_hint' function.
563-
// It accepts the compile-time properties that may include cache-hints
564-
// to be verified.
563+
// Verifies cache-hint properties from 'PropertyListT`. The parameter 'Action'
564+
// specifies the usage context.
565565
template <cache_action Action, typename PropertyListT>
566566
void check_cache_hints() {
567567
constexpr auto L1H =
@@ -576,28 +576,28 @@ void check_cache_hints() {
576576
cache_hint::streaming>() &&
577577
L2H.template is_one_of<cache_hint::cached,
578578
cache_hint::uncached>() &&
579-
!are_both(L1H, L2H, cache_hint::uncached),
579+
!are_all<cache_hint::uncached>(L1H, L2H),
580580
"unsupported cache hint");
581581
} else if constexpr (Action == cache_action::load) {
582582
static_assert(
583-
are_both(L1H, L2H, cache_hint::none) ||
583+
are_all<cache_hint::none>(L1H, L2H) ||
584584
(L1H.template is_one_of<cache_hint::uncached, cache_hint::cached,
585585
cache_hint::streaming>() &&
586586
L2H.template is_one_of<cache_hint::uncached,
587587
cache_hint::cached>()) ||
588588
(L1H == cache_hint::read_invalidate && L2H == cache_hint::cached),
589589
"unsupported cache hint");
590590
} else if constexpr (Action == cache_action::store) {
591-
static_assert(are_both(L1H, L2H, cache_hint::none) ||
592-
are_both(L1H, L2H, cache_hint::write_back) ||
591+
static_assert(are_all<cache_hint::none>(L1H, L2H) ||
592+
are_all<cache_hint::write_back>(L1H, L2H) ||
593593
(L1H.template is_one_of<cache_hint::uncached,
594594
cache_hint::write_through,
595595
cache_hint::streaming>() &&
596596
L2H.template is_one_of<cache_hint::uncached,
597597
cache_hint::write_back>()),
598598
"unsupported cache hint");
599599
} else if constexpr (Action == cache_action::atomic) {
600-
static_assert(are_both(L1H, L2H, cache_hint::none) ||
600+
static_assert(are_all<cache_hint::none>(L1H, L2H) ||
601601
(L1H == cache_hint::uncached &&
602602
L2H.template is_one_of<cache_hint::uncached,
603603
cache_hint::write_back>()),

‎sycl/include/sycl/ext/intel/esimd/memory.hpp

Lines changed: 58 additions & 88 deletions
Original file line numberDiff line numberDiff line change
@@ -95,6 +95,20 @@ ESIMD_INLINE simd<T, N> lsc_format_ret(simd<T1, N> Vals) {
9595
}
9696
}
9797

98+
/// Extracts a cache hint with the given 'Level' to pass it to
99+
/// ESIMD/GENX intrinsics. If `PropertyListT` does not have the requested
100+
/// cache-hint, then 'cache_hint::none' is returned.
101+
template <typename PropertyListT, cache_level Level>
102+
constexpr cache_hint getCacheHintForIntrin() {
103+
static_assert(Level == cache_level::L1 || Level == cache_level::L2,
104+
"ESIMD/GENX intrinsics accept only L1/L2 cache hints");
105+
if constexpr (Level == cache_level::L1) {
106+
return getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
107+
} else {
108+
return getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
109+
}
110+
}
111+
98112
/// USM pointer gather.
99113
/// Supported platforms: DG2, PVC
100114
/// VISA instruction: lsc_load.ugm
@@ -123,10 +137,8 @@ __ESIMD_API simd<T, N * NElts> gather_impl(const T *p, simd<OffsetT, N> offsets,
123137
check_lsc_vector_size<NElts>();
124138
check_lsc_data_size<T, DS>();
125139
check_cache_hints<cache_action::load, PropertyListT>();
126-
constexpr cache_hint L1H =
127-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
128-
constexpr cache_hint L2H =
129-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
140+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
141+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
130142
constexpr uint16_t AddressScale = 1;
131143
constexpr int ImmOffset = 0;
132144
constexpr lsc_data_size EDS = expand_data_size(finalize_data_size<T, DS>());
@@ -167,10 +179,8 @@ __ESIMD_API void scatter_impl(T *p, simd<Toffset, N> offsets,
167179
check_lsc_vector_size<NElts>();
168180
check_lsc_data_size<T, DS>();
169181
check_cache_hints<cache_action::store, PropertyListT>();
170-
constexpr cache_hint L1H =
171-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
172-
constexpr cache_hint L2H =
173-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
182+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
183+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
174184
constexpr uint16_t AddressScale = 1;
175185
constexpr int ImmOffset = 0;
176186
constexpr lsc_data_size EDS = expand_data_size(finalize_data_size<T, DS>());
@@ -904,10 +914,8 @@ block_load_impl(const T *p, simd_mask<1> pred, simd<T, NElts> pass_thru) {
904914
using LoadElemT = __ESIMD_DNS::__raw_t<
905915
std::conditional_t<SmallIntFactor == 1, T,
906916
std::conditional_t<Use64BitData, uint64_t, uint32_t>>>;
907-
constexpr cache_hint L1H =
908-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
909-
constexpr cache_hint L2H =
910-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
917+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
918+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
911919

912920
constexpr uint16_t AddressScale = 1;
913921
constexpr int ImmOffset = 0;
@@ -1005,10 +1013,8 @@ __ESIMD_API
10051013
using LoadElemT = __ESIMD_DNS::__raw_t<
10061014
std::conditional_t<SmallIntFactor == 1, T,
10071015
std::conditional_t<Use64BitData, uint64_t, uint32_t>>>;
1008-
constexpr cache_hint L1H =
1009-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
1010-
constexpr cache_hint L2H =
1011-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
1016+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
1017+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
10121018
constexpr uint16_t AddressScale = 1;
10131019
constexpr int ImmOffset = 0;
10141020
constexpr lsc_data_size ActualDS =
@@ -1105,10 +1111,8 @@ __ESIMD_API
11051111
using LoadElemT = __ESIMD_DNS::__raw_t<
11061112
std::conditional_t<SmallIntFactor == 1, T,
11071113
std::conditional_t<Use64BitData, uint64_t, uint32_t>>>;
1108-
constexpr cache_hint L1H =
1109-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
1110-
constexpr cache_hint L2H =
1111-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
1114+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
1115+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
11121116
constexpr uint16_t AddressScale = 1;
11131117
constexpr int ImmOffset = 0;
11141118
constexpr lsc_data_size ActualDS =
@@ -1165,10 +1169,8 @@ block_store_impl(T *p, simd<T, NElts> vals, simd_mask<1> pred) {
11651169
using StoreType = __ESIMD_DNS::__raw_t<
11661170
std::conditional_t<SmallIntFactor == 1, T,
11671171
std::conditional_t<Use64BitData, uint64_t, uint32_t>>>;
1168-
constexpr cache_hint L1H =
1169-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
1170-
constexpr cache_hint L2H =
1171-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
1172+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
1173+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
11721174
constexpr uint16_t AddressScale = 1;
11731175
constexpr int ImmOffset = 0;
11741176
constexpr lsc_data_size ActualDS =
@@ -1230,10 +1232,8 @@ __ESIMD_API
12301232
using StoreElemT = __ESIMD_DNS::__raw_t<
12311233
std::conditional_t<SmallIntFactor == 1, T,
12321234
std::conditional_t<Use64BitData, uint64_t, uint32_t>>>;
1233-
constexpr cache_hint L1H =
1234-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
1235-
constexpr cache_hint L2H =
1236-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
1235+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
1236+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
12371237
constexpr uint16_t AddressScale = 1;
12381238
constexpr int ImmOffset = 0;
12391239
constexpr lsc_data_size ActualDS =
@@ -2586,10 +2586,8 @@ scatter_impl(AccessorTy acc, simd<OffsetT, N> offsets, simd<T, N * NElts> vals,
25862586
check_lsc_vector_size<NElts>();
25872587
check_lsc_data_size<T, DS>();
25882588
check_cache_hints<cache_action::store, PropertyListT>();
2589-
constexpr cache_hint L1H =
2590-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
2591-
constexpr cache_hint L2H =
2592-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
2589+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
2590+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
25932591
constexpr uint16_t AddressScale = 1;
25942592
constexpr int ImmOffset = 0;
25952593
constexpr lsc_data_size EDS = expand_data_size(finalize_data_size<T, DS>());
@@ -2686,10 +2684,8 @@ gather_impl(AccessorT acc, simd<OffsetT, N / VS> byte_offsets,
26862684
constexpr lsc_vector_size LSCVS = to_lsc_vector_size<VS>();
26872685
constexpr auto Transposed = lsc_data_order::nontranspose;
26882686
using MsgT = typename lsc_expand_type<T>::type;
2689-
constexpr cache_hint L1H =
2690-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
2691-
constexpr cache_hint L2H =
2692-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
2687+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
2688+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
26932689
auto SI = get_surface_index(acc);
26942690
simd<uint32_t, N / VS> ByteOffsets32 = convert<uint32_t>(byte_offsets);
26952691
simd<MsgT, N> PassThruExpanded = lsc_format_input<MsgT>(pass_thru);
@@ -2793,10 +2789,8 @@ __ESIMD_API void prefetch_impl(const T *p, simd<Toffset, N> byte_offsets,
27932789
check_lsc_vector_size<NElts>();
27942790
check_lsc_data_size<T, DS>();
27952791
check_cache_hints<cache_action::prefetch, PropertyListT>();
2796-
constexpr cache_hint L1H =
2797-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
2798-
constexpr cache_hint L2H =
2799-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
2792+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
2793+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
28002794
constexpr uint16_t AddressScale = 1;
28012795
constexpr int ImmOffset = 0;
28022796
constexpr lsc_data_size EDS = expand_data_size(finalize_data_size<T, DS>());
@@ -2817,10 +2811,8 @@ prefetch_impl(const T *p, Toffset offset, simd_mask<1> pred) {
28172811
check_lsc_vector_size<NElts>();
28182812
check_lsc_data_size<T, DS>();
28192813
check_cache_hints<cache_action::prefetch, PropertyListT>();
2820-
constexpr cache_hint L1H =
2821-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
2822-
constexpr cache_hint L2H =
2823-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
2814+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
2815+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
28242816
constexpr uint16_t AddressScale = 1;
28252817
constexpr int ImmOffset = 0;
28262818
constexpr lsc_data_size EDS = finalize_data_size<T, DS>();
@@ -2872,10 +2864,8 @@ prefetch_impl(AccessorTy acc, simd<OffsetT, N> byte_offsets,
28722864
check_lsc_vector_size<NElts>();
28732865
check_lsc_data_size<T, DS>();
28742866
check_cache_hints<cache_action::prefetch, PropertyListT>();
2875-
constexpr cache_hint L1H =
2876-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
2877-
constexpr cache_hint L2H =
2878-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
2867+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
2868+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
28792869
constexpr uint16_t AddressScale = 1;
28802870
constexpr int ImmOffset = 0;
28812871
constexpr lsc_data_size EDS = expand_data_size(finalize_data_size<T, DS>());
@@ -2919,10 +2909,8 @@ prefetch_impl(AccessorTy acc, OffsetT byte_offset, simd_mask<1> pred) {
29192909
check_lsc_vector_size<NElts>();
29202910
check_lsc_data_size<T, DS>();
29212911
check_cache_hints<cache_action::prefetch, PropertyListT>();
2922-
constexpr cache_hint L1H =
2923-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
2924-
constexpr cache_hint L2H =
2925-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
2912+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
2913+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
29262914
constexpr uint16_t AddressScale = 1;
29272915
constexpr int ImmOffset = 0;
29282916
constexpr lsc_data_size EDS = finalize_data_size<T, DS>();
@@ -3058,10 +3046,8 @@ __ESIMD_API simd<T, N> load_2d_impl(const T *Ptr, unsigned SurfaceWidth,
30583046
unsigned SurfacePitch, int X, int Y) {
30593047

30603048
check_cache_hints<cache_action::load, PropertyListT>();
3061-
constexpr cache_hint L1H =
3062-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
3063-
constexpr cache_hint L2H =
3064-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
3049+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
3050+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
30653051
using RawT = __raw_t<T>;
30663052
check_lsc_block_2d_restrictions<RawT, BlockWidth, BlockHeight, NBlocks,
30673053
Transposed, Transformed, block_2d_op::load>();
@@ -3172,10 +3158,8 @@ __ESIMD_API void prefetch_2d_impl(const T *Ptr, unsigned SurfaceWidth,
31723158
check_cache_hints<cache_action::prefetch, PropertyListT>();
31733159
check_lsc_block_2d_restrictions<RawT, BlockWidth, BlockHeight, NBlocks, false,
31743160
false, block_2d_op::prefetch>();
3175-
constexpr cache_hint L1H =
3176-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
3177-
constexpr cache_hint L2H =
3178-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
3161+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
3162+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
31793163
constexpr lsc_data_size DS =
31803164
finalize_data_size<RawT, lsc_data_size::default_size>();
31813165
uintptr_t Addr = reinterpret_cast<uintptr_t>(Ptr);
@@ -3220,10 +3204,8 @@ __ESIMD_API void store_2d_impl(T *Ptr, unsigned SurfaceWidth,
32203204
using RawT = __raw_t<T>;
32213205
__ESIMD_DNS::check_cache_hints<__ESIMD_DNS::cache_action::store,
32223206
PropertyListT>();
3223-
constexpr cache_hint L1H =
3224-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
3225-
constexpr cache_hint L2H =
3226-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
3207+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
3208+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
32273209
check_lsc_block_2d_restrictions<RawT, BlockWidth, BlockHeight, 1, false,
32283210
false, block_2d_op::store>();
32293211
constexpr lsc_data_size DS =
@@ -6164,10 +6146,8 @@ atomic_update_impl(T *p, simd<Toffset, N> offsets, simd_mask<N> pred) {
61646146
check_atomic<Op, T, N, 0, /*IsLSC*/ true>();
61656147
check_lsc_data_size<T, DS>();
61666148
check_cache_hints<cache_action::atomic, PropertyListT>();
6167-
constexpr cache_hint L1H =
6168-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
6169-
constexpr cache_hint L2H =
6170-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
6149+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
6150+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
61716151
constexpr uint16_t AddressScale = 1;
61726152
constexpr int ImmOffset = 0;
61736153
constexpr lsc_data_size EDS = expand_data_size(finalize_data_size<T, DS>());
@@ -6208,10 +6188,8 @@ atomic_update_impl(T *p, simd<Toffset, N> offsets, simd<T, N> src0,
62086188
check_lsc_data_size<T, DS>();
62096189
check_atomic<Op, T, N, 1, /*IsLSC*/ true>();
62106190
check_cache_hints<cache_action::atomic, PropertyListT>();
6211-
constexpr cache_hint L1H =
6212-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
6213-
constexpr cache_hint L2H =
6214-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
6191+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
6192+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
62156193
constexpr uint16_t AddressScale = 1;
62166194
constexpr int ImmOffset = 0;
62176195
constexpr lsc_data_size EDS = expand_data_size(finalize_data_size<T, DS>());
@@ -6254,10 +6232,8 @@ atomic_update_impl(T *p, simd<Toffset, N> offsets, simd<T, N> src0,
62546232
check_lsc_data_size<T, DS>();
62556233
check_atomic<Op, T, N, 2, /*IsLSC*/ true>();
62566234
check_cache_hints<cache_action::atomic, PropertyListT>();
6257-
constexpr cache_hint L1H =
6258-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
6259-
constexpr cache_hint L2H =
6260-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
6235+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
6236+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
62616237
constexpr uint16_t AddressScale = 1;
62626238
constexpr int ImmOffset = 0;
62636239
constexpr lsc_data_size EDS = expand_data_size(finalize_data_size<T, DS>());
@@ -6310,10 +6286,8 @@ __ESIMD_API
63106286
check_lsc_data_size<T, DS>();
63116287
check_atomic<Op, T, N, 0, /*IsLSC*/ true>();
63126288
check_cache_hints<cache_action::atomic, PropertyListT>();
6313-
constexpr cache_hint L1H =
6314-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
6315-
constexpr cache_hint L2H =
6316-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
6289+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
6290+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
63176291
constexpr uint16_t AddressScale = 1;
63186292
constexpr int ImmOffset = 0;
63196293
constexpr lsc_data_size EDS = expand_data_size(finalize_data_size<T, DS>());
@@ -6365,10 +6339,8 @@ __ESIMD_API
63656339
check_lsc_data_size<T, DS>();
63666340
check_atomic<Op, T, N, 1, /*IsLSC*/ true>();
63676341
check_cache_hints<cache_action::atomic, PropertyListT>();
6368-
constexpr cache_hint L1H =
6369-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
6370-
constexpr cache_hint L2H =
6371-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
6342+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
6343+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
63726344
constexpr uint16_t AddressScale = 1;
63736345
constexpr int ImmOffset = 0;
63746346
constexpr lsc_data_size EDS = expand_data_size(finalize_data_size<T, DS>());
@@ -6422,10 +6394,8 @@ __ESIMD_API
64226394
check_lsc_data_size<T, DS>();
64236395
check_atomic<Op, T, N, 2, /*IsLSC*/ true>();
64246396
check_cache_hints<cache_action::atomic, PropertyListT>();
6425-
constexpr cache_hint L1H =
6426-
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
6427-
constexpr cache_hint L2H =
6428-
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
6397+
constexpr auto L1H = getCacheHintForIntrin<PropertyListT, cache_level::L1>();
6398+
constexpr auto L2H = getCacheHintForIntrin<PropertyListT, cache_level::L2>();
64296399
constexpr uint16_t AddressScale = 1;
64306400
constexpr int ImmOffset = 0;
64316401
constexpr lsc_data_size EDS = expand_data_size(finalize_data_size<T, DS>());

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