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1 parent a0c8c50 commit 261290bCopy full SHA for 261290b
sycl/include/sycl/ext/intel/esimd/memory.hpp
@@ -894,7 +894,9 @@ enum fence_mask : uint8_t {
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local_barrier = 0x20,
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/// Flush L1 read - only data cache.
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l1_flush_ro_data = 0x40,
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- /// Enable thread scheduling barrier.
+ /// Creates a software (compiler) barrier, which does not generate
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+ /// any instruction and only prevents instruction scheduler from
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+ /// reordering instructions across this barrier at compile time.
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sw_barrier = 0x80
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};
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