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iclsrc
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Merge from 'sycl' to 'sycl-web'
2 parents a9bcb4f + a038480 commit 26f5fb4

39 files changed

+1825
-184
lines changed

‎buildbot/configure.py

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -55,8 +55,6 @@ def do_configure(args):
5555
"-DLLVM_EXTERNAL_XPTI_SOURCE_DIR={}".format(xpti_dir),
5656
"-DLLVM_ENABLE_PROJECTS={}".format(llvm_enable_projects),
5757
"-DLIBCLC_TARGETS_TO_BUILD={}".format(libclc_targets_to_build),
58-
"-DOpenCL_INCLUDE_DIR={}".format(ocl_header_dir),
59-
"-DOpenCL_LIBRARY={}".format(icd_loader_lib),
6058
"-DSYCL_BUILD_PI_CUDA={}".format(sycl_build_pi_cuda),
6159
"-DLLVM_BUILD_TOOLS=ON",
6260
"-DSYCL_ENABLE_WERROR=ON",

‎clang/lib/Driver/Driver.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4751,9 +4751,11 @@ Action *Driver::ConstructPhaseAction(
47514751
return C.MakeAction<BackendJobAction>(Input, Output);
47524752
}
47534753
if (Args.hasArg(options::OPT_fsycl_device_only)) {
4754+
types::ID OutputType =
4755+
Args.hasArg(options::OPT_S) ? types::TY_LLVM_IR : types::TY_LLVM_BC;
47544756
if (Args.hasFlag(options::OPT_fsycl_use_bitcode,
47554757
options::OPT_fno_sycl_use_bitcode, true))
4756-
return C.MakeAction<BackendJobAction>(Input, types::TY_LLVM_BC);
4758+
return C.MakeAction<BackendJobAction>(Input, OutputType);
47574759
// Use of -fsycl-device-only creates a bitcode file, we need to translate
47584760
// that to a SPIR-V file with -fno-sycl-use-bitcode
47594761
auto *BackendAction =

‎clang/test/Driver/sycl.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@
2323

2424
// RUN: %clang -### -fsycl-device-only -c %s 2>&1 | FileCheck %s --check-prefix=DEFAULT
2525
// RUN: %clang -### -fsycl-device-only %s 2>&1 | FileCheck %s --check-prefix=DEFAULT
26+
// RUN: %clang -### -fsycl-device-only -S %s 2>&1 | FileCheck %s --check-prefix=TEXTUAL
2627
// RUN: %clang -### -fsycl-device-only -fsycl %s 2>&1 | FileCheck %s --check-prefix=DEFAULT
2728
// RUN: %clang -### -fsycl-device-only -fno-sycl-use-bitcode -c %s 2>&1 | FileCheck %s --check-prefix=NO-BITCODE
2829
// RUN: %clang -### -target spir64-unknown-linux-sycldevice -c -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=TARGET
@@ -39,6 +40,7 @@
3940
// NO-BITCODE: "{{.*}}llvm-spirv"{{.*}} "-spirv-max-version=1.1"{{.*}} "-spirv-ext=+all"
4041
// TARGET: "-triple" "spir64-unknown-linux-sycldevice"{{.*}} "-fsycl-is-device"{{.*}} "-emit-llvm-bc"
4142
// COMBINED: "-triple" "spir64-unknown-{{.*}}-sycldevice"{{.*}} "-fsycl-is-device"{{.*}} "-emit-llvm-bc"
43+
// TEXTUAL: "-triple" "spir64-unknown-{{.*}}-sycldevice{{.*}}" "-fsycl-is-device"{{.*}} "-emit-llvm"
4244

4345
/// Verify -fsycl-device-only phases
4446
// RUN: %clang -### -ccc-print-phases -fsycl-device-only %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES

‎clang/tools/driver/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ set( LLVM_LINK_COMPONENTS
1313
Option
1414
ScalarOpts
1515
Support
16+
SYCLLowerIR
1617
TransformUtils
1718
Vectorize
1819
)

‎llvm-spirv/include/LLVMSPIRVExtensions.inc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,3 +14,4 @@ EXT(SPV_INTEL_fpga_reg)
1414
EXT(SPV_INTEL_blocking_pipes)
1515
EXT(SPV_INTEL_function_pointers)
1616
EXT(SPV_INTEL_kernel_attributes)
17+
EXT(SPV_INTEL_io_pipes)

‎llvm-spirv/lib/SPIRV/SPIRVReader.cpp

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3046,8 +3046,17 @@ void SPIRVToLLVM::transIntelFPGADecorations(SPIRVValue *BV, Value *V) {
30463046
SmallString<256> AnnotStr;
30473047
generateIntelFPGAAnnotation(BV, AnnotStr);
30483048

3049-
if (AnnotStr.empty())
3049+
if (AnnotStr.empty()) {
3050+
// Check if IO pipe decoration is applied to the global
3051+
SPIRVWord ID;
3052+
if (BV->hasDecorate(DecorationIOPipeStorageINTEL, 0, &ID)) {
3053+
auto Literals = BV->getDecorationLiterals(DecorationIOPipeStorageINTEL);
3054+
assert(Literals.size() == 1 &&
3055+
"IO PipeStorage decoration shall have 1 extra operand");
3056+
GV->setMetadata("io_pipe_id", getMDNodeStringIntVec(Context, Literals));
3057+
}
30503058
return;
3059+
}
30513060

30523061
Constant *StrConstant =
30533062
ConstantDataArray::getString(*Context, StringRef(AnnotStr));

‎llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

Lines changed: 47 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -779,9 +779,9 @@ class LLVMParallelAccessIndices {
779779
/// Go through the operands !llvm.loop metadata attached to the branch
780780
/// instruction, fill the Loop Control mask and possible parameters for its
781781
/// fields.
782-
static spv::LoopControlMask
783-
getLoopControl(const BranchInst *Branch, std::vector<SPIRVWord> &Parameters,
784-
LLVMToSPIRV::LLVMToSPIRVMetadataMap &IndexGroupArrayMap) {
782+
spv::LoopControlMask
783+
LLVMToSPIRV::getLoopControl(const BranchInst *Branch,
784+
std::vector<SPIRVWord> &Parameters) {
785785
if (!Branch)
786786
return spv::LoopControlMaskNone;
787787
MDNode *LoopMD = Branch->getMetadata("llvm.loop");
@@ -821,26 +821,34 @@ getLoopControl(const BranchInst *Branch, std::vector<SPIRVWord> &Parameters,
821821
size_t I = getMDOperandAsInt(Node, 1);
822822
Parameters.push_back(I);
823823
LoopControl |= spv::LoopControlDependencyLengthMask;
824-
} else if (S == "llvm.loop.ii.count") {
825-
size_t I = getMDOperandAsInt(Node, 1);
826-
Parameters.push_back(I);
827-
LoopControl |= spv::LoopControlInitiationIntervalINTEL;
828-
} else if (S == "llvm.loop.max_concurrency.count") {
829-
size_t I = getMDOperandAsInt(Node, 1);
830-
Parameters.push_back(I);
831-
LoopControl |= spv::LoopControlMaxConcurrencyINTEL;
832-
} else if (S == "llvm.loop.parallel_access_indices") {
833-
// Intel FPGA IVDep loop attribute
834-
LLVMParallelAccessIndices IVDep(Node, IndexGroupArrayMap);
835-
IVDep.initialize();
836-
// Store IVDep-specific parameters into an intermediate
837-
// container to address the case when there're multiple
838-
// IVDep metadata nodes and this condition gets entered multiple
839-
// times. The update of the main parameters vector & the loop control
840-
// mask will be done later, in the main scope of the function
841-
unsigned SafeLen = IVDep.getSafeLen();
842-
for (auto &ArrayId : IVDep.getArrayVariables())
843-
DependencyArrayParameters.emplace_back(ArrayId, SafeLen);
824+
} else if (BM->isAllowedToUseExtension(
825+
ExtensionID::SPV_INTEL_fpga_loop_controls)) {
826+
// Add Intel specific Loop Control masks
827+
if (S == "llvm.loop.ii.count") {
828+
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
829+
BM->addCapability(CapabilityFPGALoopControlsINTEL);
830+
size_t I = getMDOperandAsInt(Node, 1);
831+
Parameters.push_back(I);
832+
LoopControl |= spv::LoopControlInitiationIntervalINTEL;
833+
} else if (S == "llvm.loop.max_concurrency.count") {
834+
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
835+
BM->addCapability(CapabilityFPGALoopControlsINTEL);
836+
size_t I = getMDOperandAsInt(Node, 1);
837+
Parameters.push_back(I);
838+
LoopControl |= spv::LoopControlMaxConcurrencyINTEL;
839+
} else if (S == "llvm.loop.parallel_access_indices") {
840+
// Intel FPGA IVDep loop attribute
841+
LLVMParallelAccessIndices IVDep(Node, IndexGroupArrayMap);
842+
IVDep.initialize();
843+
// Store IVDep-specific parameters into an intermediate
844+
// container to address the case when there're multiple
845+
// IVDep metadata nodes and this condition gets entered multiple
846+
// times. The update of the main parameters vector & the loop control
847+
// mask will be done later, in the main scope of the function
848+
unsigned SafeLen = IVDep.getSafeLen();
849+
for (auto &ArrayId : IVDep.getArrayVariables())
850+
DependencyArrayParameters.emplace_back(ArrayId, SafeLen);
851+
}
844852
}
845853
}
846854
}
@@ -855,6 +863,8 @@ getLoopControl(const BranchInst *Branch, std::vector<SPIRVWord> &Parameters,
855863
Parameters.push_back(ArraySflnPair.first);
856864
Parameters.push_back(ArraySflnPair.second);
857865
}
866+
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
867+
BM->addCapability(CapabilityFPGALoopControlsINTEL);
858868
LoopControl |= spv::LoopControlDependencyArrayINTEL;
859869
}
860870

@@ -1066,8 +1076,7 @@ SPIRVValue *LLVMToSPIRV::transValueWithoutDecoration(Value *V,
10661076
/// with true edge going to the header and the false edge going out of
10671077
/// the loop, which corresponds to a "Merge Block" per the SPIR-V spec.
10681078
std::vector<SPIRVWord> Parameters;
1069-
spv::LoopControlMask LoopControl =
1070-
getLoopControl(Branch, Parameters, IndexGroupArrayMap);
1079+
spv::LoopControlMask LoopControl = getLoopControl(Branch, Parameters);
10711080

10721081
if (Branch->isUnconditional()) {
10731082
// For "for" and "while" loops llvm.loop metadata is attached to
@@ -1902,10 +1911,23 @@ void LLVMToSPIRV::transGlobalAnnotation(GlobalVariable *V) {
19021911
}
19031912
}
19041913

1914+
void LLVMToSPIRV::transGlobalIOPipeStorage(GlobalVariable *V, MDNode *IO) {
1915+
SPIRVDBG(dbgs() << "[transGlobalIOPipeStorage] " << *V << '\n');
1916+
SPIRVValue *SV = transValue(V, nullptr);
1917+
assert(SV && "Failed to process OCL PipeStorage object");
1918+
if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_io_pipes)) {
1919+
BM->addCapability(CapabilityIOPipeINTEL);
1920+
unsigned ID = getMDOperandAsInt(IO, 0);
1921+
SV->addDecorate(DecorationIOPipeStorageINTEL, ID);
1922+
}
1923+
}
1924+
19051925
bool LLVMToSPIRV::transGlobalVariables() {
19061926
for (auto I = M->global_begin(), E = M->global_end(); I != E; ++I) {
19071927
if ((*I).getName() == "llvm.global.annotations")
19081928
transGlobalAnnotation(&(*I));
1929+
else if (MDNode *IO = ((*I).getMetadata("io_pipe_id")))
1930+
transGlobalIOPipeStorage(&(*I), IO);
19091931
else if (!transValue(&(*I), nullptr))
19101932
return false;
19111933
}

‎llvm-spirv/lib/SPIRV/SPIRVWriter.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,9 @@ class LLVMToSPIRV : public ModulePass {
8585

8686
SPIRVValue *getTranslatedValue(const Value *) const;
8787

88+
spv::LoopControlMask getLoopControl(const BranchInst *Branch,
89+
std::vector<SPIRVWord> &Parameters);
90+
8891
// Translation functions
8992
bool transAddressingMode();
9093
bool transAlign(Value *V, SPIRVValue *BV);
@@ -113,6 +116,7 @@ class LLVMToSPIRV : public ModulePass {
113116
void transGlobalAnnotation(GlobalVariable *V);
114117
SPIRVValue *transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
115118
bool CreateForward = true);
119+
void transGlobalIOPipeStorage(GlobalVariable *V, MDNode *IO);
116120

117121
typedef DenseMap<Type *, SPIRVType *> LLVMToSPIRVTypeMap;
118122
typedef DenseMap<Value *, SPIRVValue *> LLVMToSPIRVValueMap;

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVDecorate.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,8 @@ class SPIRVDecorate : public SPIRVDecorateGeneric {
156156
return getSet(ExtensionID::SPV_INTEL_fpga_memory_attributes);
157157
case DecorationReferencedIndirectlyINTEL:
158158
return getSet(ExtensionID::SPV_INTEL_function_pointers);
159+
case DecorationIOPipeStorageINTEL:
160+
return getSet(ExtensionID::SPV_INTEL_io_pipes);
159161
default:
160162
return SPIRVExtSet();
161163
}
@@ -251,6 +253,8 @@ class SPIRVMemberDecorate : public SPIRVDecorateGeneric {
251253
case DecorationMergeINTEL:
252254
case DecorationBankBitsINTEL:
253255
return getSet(ExtensionID::SPV_INTEL_fpga_memory_attributes);
256+
case DecorationIOPipeStorageINTEL:
257+
return getSet(ExtensionID::SPV_INTEL_io_pipes);
254258
default:
255259
return SPIRVExtSet();
256260
}

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -365,6 +365,7 @@ template <> inline void SPIRVMap<Decoration, SPIRVCapVec>::init() {
365365
ADD_VEC_INIT(DecorationBankBitsINTEL, {CapabilityFPGAMemoryAttributesINTEL});
366366
ADD_VEC_INIT(DecorationReferencedIndirectlyINTEL,
367367
{CapabilityIndirectReferencesINTEL});
368+
ADD_VEC_INIT(DecorationIOPipeStorageINTEL, {CapabilityIOPipeINTEL});
368369
}
369370

370371
template <> inline void SPIRVMap<BuiltIn, SPIRVCapVec>::init() {

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -348,6 +348,7 @@ template <> inline void SPIRVMap<Decoration, std::string>::init() {
348348
add(DecorationMergeINTEL, "MergeINTEL");
349349
add(DecorationBankBitsINTEL, "BankBitsINTEL");
350350
add(DecorationReferencedIndirectlyINTEL, "ReferencedIndirectlyINTEL");
351+
add(DecorationIOPipeStorageINTEL, "IOPipeStorageINTEL");
351352
}
352353
SPIRV_DEF_NAMEMAP(Decoration, SPIRVDecorationNameMap)
353354

@@ -502,6 +503,7 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
502503
add(CapabilityIndirectReferencesINTEL, "IndirectReferencesINTEL");
503504
add(CapabilityKernelAttributesINTEL, "KernelAttributesINTEL");
504505
add(CapabilityFPGAKernelAttributesINTEL, "FPGAKernelAttributesINTEL");
506+
add(CapabilityIOPipeINTEL, "IOPipeINTEL");
505507
}
506508
SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap)
507509

‎llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -405,6 +405,7 @@ enum Decoration {
405405
DecorationSimpleDualPortINTEL = 5833,
406406
DecorationMergeINTEL = 5834,
407407
DecorationBankBitsINTEL = 5835,
408+
DecorationIOPipeStorageINTEL = 5944,
408409
DecorationMax = 0x7fffffff,
409410
};
410411

@@ -690,6 +691,7 @@ enum Capability {
690691
CapabilityFPGARegINTEL = 5948,
691692
CapabilityKernelAttributesINTEL= 5892,
692693
CapabilityFPGAKernelAttributesINTEL= 5897,
694+
CapabilityIOPipeINTEL = 5943,
693695
CapabilityMax = 0x7fffffff,
694696
};
695697

‎llvm-spirv/test/PipeStorageIOINTEL.ll

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
1+
; RUN: llvm-as %s -o %t.bc
2+
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_io_pipes -o %t.spv
3+
; RUN: llvm-spirv %t.spv -to-text -o %t.spt
4+
; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
5+
6+
; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
7+
; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
8+
9+
; RUN: llvm-spirv -spirv-text -r %t.spt -o %t.rev.bc
10+
; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
11+
12+
; CHECK-LLVM: %spirv.ConstantPipeStorage = type { i32, i32, i32 }
13+
; CHECK-LLVM: %"[[CL_PIPE_STORAGE_NAME:[^"]+]]" = type { %spirv.PipeStorage addrspace(1)* }
14+
; CHECK-LLVM: %spirv.PipeStorage = type opaque
15+
; CHECK-LLVM: [[CREATOR_NAME:[^ ]+]] = linkonce_odr addrspace(1) global %spirv.ConstantPipeStorage { i32 16, i32 16, i32 1 }, align 4
16+
; CHECK-LLVM: @mygpipe = addrspace(1) global %"[[CL_PIPE_STORAGE_NAME]]" { %spirv.PipeStorage addrspace(1)* bitcast (%spirv.ConstantPipeStorage addrspace(1)* [[CREATOR_NAME]] to %spirv.PipeStorage addrspace(1)*) }, align 4, !io_pipe_id ![[IO_MD:[0-9]+]]
17+
; CHECK-LLVM: ![[IO_MD]] = !{i32 1}
18+
19+
; CHECK-SPIRV: 2 Capability PipeStorage
20+
; CHECK-SPIRV: 2 Capability IOPipeINTEL
21+
; CHECK-SPIRV: 6 Extension "SPV_INTEL_io_pipes"
22+
23+
; CHECK-SPIRV: 4 Name [[MYPIPE_ID:[0-9]+]] "mygpipe"
24+
; CHECK-SPIRV: 4 Decorate [[MYPIPE_ID]] IOPipeStorageINTEL 1
25+
26+
; CHECK-SPIRV: 2 TypePipeStorage [[PIPE_STORAGE_ID:[0-9]+]]
27+
; CHECK-SPIRV-NEXT: 2 TypePipeStorage [[PIPE_STORAGE_ID_2:[0-9]+]]
28+
; CHECK-SPIRV: 3 TypeStruct [[CL_PIPE_STORAGE_ID:[0-9]+]] [[PIPE_STORAGE_ID_2]]
29+
; CHECK-SPIRV: 4 TypePointer [[CL_PIPE_STORAGE_PTR_ID:[0-9]+]] 5 [[CL_PIPE_STORAGE_ID]]
30+
31+
; CHECK-SPIRV: 6 ConstantPipeStorage [[PIPE_STORAGE_ID]] [[CPS_ID:[0-9]+]] 16 16 1
32+
; CHECK-SPIRV: 4 ConstantComposite [[CL_PIPE_STORAGE_ID]] [[COMPOSITE_ID:[0-9]+]] [[CPS_ID]]
33+
; CHECK-SPIRV: 5 Variable [[CL_PIPE_STORAGE_PTR_ID]] [[MYPIPE_ID]] 5 [[COMPOSITE_ID]]
34+
35+
target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
36+
target triple = "spir-unknown-unknown"
37+
38+
%spirv.ConstantPipeStorage = type { i32, i32, i32 }
39+
%"class.cl::pipe_storage<int __attribute__((ext_vector_type(4))), 1>" = type { %spirv.PipeStorage addrspace(1)* }
40+
%spirv.PipeStorage = type opaque
41+
42+
@_ZN2cl9__details29OpConstantPipeStorage_CreatorILi16ELi16ELi1EE5valueE = linkonce_odr addrspace(1) global %spirv.ConstantPipeStorage { i32 16, i32 16, i32 1 }, align 4
43+
@mygpipe = addrspace(1) global %"class.cl::pipe_storage<int __attribute__((ext_vector_type(4))), 1>" { %spirv.PipeStorage addrspace(1)* bitcast (%spirv.ConstantPipeStorage addrspace(1)* @_ZN2cl9__details29OpConstantPipeStorage_CreatorILi16ELi16ELi1EE5valueE to %spirv.PipeStorage addrspace(1)*) }, align 4, !io_pipe_id !5
44+
45+
; Function Attrs: nounwind
46+
define spir_kernel void @worker() {
47+
entry:
48+
ret void
49+
}
50+
51+
!opencl.enable.FP_CONTRACT = !{}
52+
!opencl.spir.version = !{!0}
53+
!opencl.ocl.version = !{!1}
54+
!opencl.used.extensions = !{!2}
55+
!opencl.used.optional.core.features = !{!2}
56+
!opencl.compiler.options = !{!2}
57+
!llvm.ident = !{!3}
58+
!spirv.Source = !{!4}
59+
!spirv.String = !{}
60+
61+
!0 = !{i32 1, i32 2}
62+
!1 = !{i32 2, i32 2}
63+
!2 = !{}
64+
!3 = !{!"clang version 3.6.1 "}
65+
!4 = !{i32 4, i32 202000}
66+
!5 = !{i32 1}

‎llvm-spirv/test/transcoding/FPGAIVDepLoopAttr.ll

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@
5252
; }
5353

5454
; RUN: llvm-as < %s > %t.bc
55-
; RUN: llvm-spirv %t.bc -o %t.spv
55+
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_fpga_loop_controls -o %t.spv
5656
; RUN: llvm-spirv -to-text %t.spv -o %t.spt
5757
; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
5858

@@ -72,6 +72,9 @@ target triple = "spir64-unknown-unknown-sycldevice"
7272

7373
%"class._ZTSZ4mainE3$_0.anon" = type { i8 }
7474

75+
; CHECK-SPIRV: 2 Capability FPGALoopControlsINTEL
76+
; CHECK-SPIRV: 9 Extension "SPV_INTEL_fpga_loop_controls"
77+
7578
; CHECK-SPIRV-DAG: TypeInt [[TYPE_INT_64:[0-9]+]] 64 0
7679
; CHECK-SPIRV-DAG: TypeInt [[TYPE_INT_32:[0-9]+]] 32 0
7780
; CHECK-SPIRV-DAG: Constant [[TYPE_INT_64]] [[SIZE:[0-9]+]] 10 0

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