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[RISCV] Simplify code in decomposeMulByConstant. NFC (#100946)
We already checked that the type is a scalar integer, so the constant node should definitely be a ConstantSDNode. We can use cast instead of dyn_cast.
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -21181,37 +21181,37 @@ bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned)
2118121181
bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
2118221182
SDValue C) const {
2118321183
// Check integral scalar types.
21184-
const bool HasZmmul = Subtarget.hasStdExtZmmul();
2118521184
if (!VT.isScalarInteger())
2118621185
return false;
2118721186

2118821187
// Omit the optimization if the sub target has the M extension and the data
2118921188
// size exceeds XLen.
21189+
const bool HasZmmul = Subtarget.hasStdExtZmmul();
2119021190
if (HasZmmul && VT.getSizeInBits() > Subtarget.getXLen())
2119121191
return false;
2119221192

21193-
if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {
21194-
// Break the MUL to a SLLI and an ADD/SUB.
21195-
const APInt &Imm = ConstNode->getAPIntValue();
21196-
if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() ||
21197-
(1 - Imm).isPowerOf2() || (-1 - Imm).isPowerOf2())
21198-
return true;
21193+
auto *ConstNode = cast<ConstantSDNode>(C);
21194+
const APInt &Imm = ConstNode->getAPIntValue();
2119921195

21200-
// Optimize the MUL to (SH*ADD x, (SLLI x, bits)) if Imm is not simm12.
21201-
if (Subtarget.hasStdExtZba() && !Imm.isSignedIntN(12) &&
21202-
((Imm - 2).isPowerOf2() || (Imm - 4).isPowerOf2() ||
21203-
(Imm - 8).isPowerOf2()))
21204-
return true;
21196+
// Break the MUL to a SLLI and an ADD/SUB.
21197+
if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() ||
21198+
(1 - Imm).isPowerOf2() || (-1 - Imm).isPowerOf2())
21199+
return true;
2120521200

21206-
// Break the MUL to two SLLI instructions and an ADD/SUB, if Imm needs
21207-
// a pair of LUI/ADDI.
21208-
if (!Imm.isSignedIntN(12) && Imm.countr_zero() < 12 &&
21209-
ConstNode->hasOneUse()) {
21210-
APInt ImmS = Imm.ashr(Imm.countr_zero());
21211-
if ((ImmS + 1).isPowerOf2() || (ImmS - 1).isPowerOf2() ||
21212-
(1 - ImmS).isPowerOf2())
21213-
return true;
21214-
}
21201+
// Optimize the MUL to (SH*ADD x, (SLLI x, bits)) if Imm is not simm12.
21202+
if (Subtarget.hasStdExtZba() && !Imm.isSignedIntN(12) &&
21203+
((Imm - 2).isPowerOf2() || (Imm - 4).isPowerOf2() ||
21204+
(Imm - 8).isPowerOf2()))
21205+
return true;
21206+
21207+
// Break the MUL to two SLLI instructions and an ADD/SUB, if Imm needs
21208+
// a pair of LUI/ADDI.
21209+
if (!Imm.isSignedIntN(12) && Imm.countr_zero() < 12 &&
21210+
ConstNode->hasOneUse()) {
21211+
APInt ImmS = Imm.ashr(Imm.countr_zero());
21212+
if ((ImmS + 1).isPowerOf2() || (ImmS - 1).isPowerOf2() ||
21213+
(1 - ImmS).isPowerOf2())
21214+
return true;
2121521215
}
2121621216

2121721217
return false;

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