1
- :extension_name: SPV_INTEL_tensor_float32_conversion
2
- :capability_tf32_conversion_name: TensorFloat32ConversionINTEL
3
- :capability_tf32_conversion_token : 6425
4
- :ConvertFToTF32_name: OpConvertFToTF32INTEL
5
- :ConvertFToTF32_token : 6426
1
+ :extension_name: SPV_INTEL_tensor_float32_rounding
2
+ :capability_tf32_rounding_name: TensorFloat32RoundingINTEL
3
+ :capability_tf32_rounding_token : 6425
4
+ :RoundFToTF32_name: OpRoundFToTF32INTEL
5
+ :RoundFToTF32_token : 6426
6
6
7
7
{extension_name}
8
8
================
@@ -26,7 +26,7 @@ https://github.com/intel/llvm
26
26
27
27
== Notice
28
28
29
- Copyright (c) 2022 Intel Corporation. All rights reserved.
29
+ Copyright (c) 2023 Intel Corporation. All rights reserved.
30
30
31
31
== Status
32
32
@@ -46,8 +46,8 @@ please let us know!
46
46
47
47
[width="40%",cols="25,25"]
48
48
|========================================
49
- | Last Modified Date | {docdate}
50
- | Revision | 1
49
+ | Last Modified Date | 2023-02-09
50
+ | Revision | 2
51
51
|========================================
52
52
53
53
== Dependencies
@@ -59,7 +59,7 @@ This extension requires SPIR-V 1.0.
59
59
60
60
== Overview
61
61
62
- This extension adds conversion instruction from float to tensor float (TF32)
62
+ This extension adds rounding instruction from float to tensor float (TF32)
63
63
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits for a
64
64
fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
65
65
instruction below uses 32-bit float type to represent TF32 value.
@@ -82,16 +82,16 @@ This extension introduces new capabilities:
82
82
83
83
[subs="attributes"]
84
84
----
85
- {capability_tf32_conversion_name }
85
+ {capability_tf32_rounding_name }
86
86
----
87
87
88
88
== New Instructions
89
89
90
- Instructions added under the *{capability_tf32_conversion_name }* capability:
90
+ Instructions added under the *{capability_tf32_rounding_name }* capability:
91
91
92
92
[subs="attributes"]
93
93
----
94
- {ConvertFToTF32_name }
94
+ {RoundFToTF32_name }
95
95
----
96
96
97
97
@@ -101,8 +101,8 @@ Instructions added under the *{capability_tf32_conversion_name}* capability:
101
101
[cols="70%,30%"]
102
102
[grid="rows"]
103
103
|====
104
- |*{capability_tf32_conversion_name }* | {capability_tf32_conversion_token }
105
- |{ConvertFToTF32_name } | {ConvertFToTF32_token }
104
+ |*{capability_tf32_rounding_name }* | {capability_tf32_rounding_token }
105
+ |{RoundFToTF32_name } | {RoundFToTF32_token }
106
106
|====
107
107
108
108
== Modifications to the SPIR-V Specification, Version 1.6
@@ -115,7 +115,7 @@ Modify Section 3.31, Capability, adding rows to the Capability table:
115
115
[options="header"]
116
116
|====
117
117
2+^| Capability ^| Implicitly Declares
118
- | {capability_tf32_conversion_token } | *{capability_tf32_conversion_name }*
118
+ | {capability_tf32_rounding_token } | *{capability_tf32_rounding_name }*
119
119
| Enables a rounding instruction from float to tf32 data format +
120
120
+
121
121
See also extension: *{extension_name}*
@@ -125,25 +125,29 @@ See also extension: *{extension_name}*
125
125
126
126
=== Instructions
127
127
128
- ==== 3.37 .11. Conversion Instructions
128
+ ==== 3.42 .11. Conversion Instructions
129
129
130
130
[cols="1,1,3*3",width="100%"]
131
131
|=====
132
- 4+|[[OpConvertFToTF32 ]]*{ConvertFToTF32_name }* +
132
+ 4+|[[OpRoundFToTF32 ]]*{RoundFToTF32_name }* +
133
133
+
134
- Convert value numerically from a floating point type to *TF32*.
134
+ Convert value numerically from a 32-bit floating point type to *TF32*.
135
135
It rounds up 13th bit of a float value and zero out last 13 bits. +
136
136
+
137
- 'Result Type' must be a scalar or vector of floating-point type. +
137
+ 'Result Type' must be a scalar or vector of 32-bit floating-point type. +
138
138
+
139
- 'Float Value' must be a scalar or vector of floating-point type.
140
- It must have the same number of components as Result Type. +
139
+ 'Float Value' must have the same type as 'Result Type'. +
140
+ +
141
+ If 'Float Value' is an infinity, the result is the same infinity. If 'Float Value'
142
+ is a NaN, the result is a NaN, but not necessarily the same NaN. +
143
+ +
144
+ The *RelaxedPrecision* <<Decoration,Decoration>> has no effect on this instruction. +
141
145
+
142
146
Results are computed per component. +
143
147
+
144
148
1+|Capability: +
145
- *{capability_tf32_conversion_name }*
146
- 1+| 4 | {ConvertFToTF32_token }
149
+ *{capability_tf32_rounding_name }*
150
+ 1+| 4 | {RoundFToTF32_token }
147
151
| '<id>' +
148
152
'Result Type'
149
153
| 'Result <id>'
@@ -169,4 +173,5 @@ Results are computed per component. +
169
173
|========================================
170
174
|Rev|Date|Author|Changes
171
175
|1|2022-08-22|Dmitry Sidorov|Initial revision
176
+ |2|2023-02-09|Dmitry Sidorov| Rename the instruction and the extension
172
177
|========================================
0 commit comments