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Update the spec
Signed-off-by: Sidorov, Dmitry <[email protected]>
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sycl/doc/design/spirv-extensions/SPV_INTEL_tensor_float32_conversion.asciidoc renamed to sycl/doc/design/spirv-extensions/SPV_INTEL_tensor_float32_rounding.asciidoc

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:extension_name: SPV_INTEL_tensor_float32_conversion
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:capability_tf32_conversion_name: TensorFloat32ConversionINTEL
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:capability_tf32_conversion_token: 6425
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:ConvertFToTF32_name: OpConvertFToTF32INTEL
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:ConvertFToTF32_token: 6426
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:extension_name: SPV_INTEL_tensor_float32_rounding
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:capability_tf32_rounding_name: TensorFloat32RoundingINTEL
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:capability_tf32_rounding_token: 6425
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:RoundFToTF32_name: OpRoundFToTF32INTEL
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:RoundFToTF32_token: 6426
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{extension_name}
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================
@@ -26,7 +26,7 @@ https://github.com/intel/llvm
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== Notice
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Copyright (c) 2022 Intel Corporation. All rights reserved.
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Copyright (c) 2023 Intel Corporation. All rights reserved.
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== Status
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@@ -46,8 +46,8 @@ please let us know!
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[width="40%",cols="25,25"]
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|========================================
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| Last Modified Date | {docdate}
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| Revision | 1
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| Last Modified Date | 2023-02-09
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| Revision | 2
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|========================================
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== Dependencies
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== Overview
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This extension adds conversion instruction from float to tensor float (TF32)
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This extension adds rounding instruction from float to tensor float (TF32)
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data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits for a
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fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
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instruction below uses 32-bit float type to represent TF32 value.
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[subs="attributes"]
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----
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{capability_tf32_conversion_name}
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{capability_tf32_rounding_name}
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----
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== New Instructions
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Instructions added under the *{capability_tf32_conversion_name}* capability:
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Instructions added under the *{capability_tf32_rounding_name}* capability:
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[subs="attributes"]
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----
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{ConvertFToTF32_name}
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{RoundFToTF32_name}
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----
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[cols="70%,30%"]
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[grid="rows"]
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|====
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|*{capability_tf32_conversion_name}* | {capability_tf32_conversion_token}
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|{ConvertFToTF32_name} | {ConvertFToTF32_token}
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|*{capability_tf32_rounding_name}* | {capability_tf32_rounding_token}
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|{RoundFToTF32_name} | {RoundFToTF32_token}
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|====
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== Modifications to the SPIR-V Specification, Version 1.6
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[options="header"]
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|====
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2+^| Capability ^| Implicitly Declares
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| {capability_tf32_conversion_token} | *{capability_tf32_conversion_name}*
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| {capability_tf32_rounding_token} | *{capability_tf32_rounding_name}*
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| Enables a rounding instruction from float to tf32 data format +
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See also extension: *{extension_name}*
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=== Instructions
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==== 3.37.11. Conversion Instructions
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==== 3.42.11. Conversion Instructions
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[cols="1,1,3*3",width="100%"]
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|=====
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4+|[[OpConvertFToTF32]]*{ConvertFToTF32_name}* +
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4+|[[OpRoundFToTF32]]*{RoundFToTF32_name}* +
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+
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Convert value numerically from a floating point type to *TF32*.
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Convert value numerically from a 32-bit floating point type to *TF32*.
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It rounds up 13th bit of a float value and zero out last 13 bits. +
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'Result Type' must be a scalar or vector of floating-point type. +
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'Result Type' must be a scalar or vector of 32-bit floating-point type. +
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'Float Value' must be a scalar or vector of floating-point type.
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It must have the same number of components as Result Type. +
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'Float Value' must have the same type as 'Result Type'. +
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+
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If 'Float Value' is an infinity, the result is the same infinity. If 'Float Value'
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is a NaN, the result is a NaN, but not necessarily the same NaN. +
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+
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The *RelaxedPrecision* <<Decoration,Decoration>> has no effect on this instruction. +
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Results are computed per component. +
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1+|Capability: +
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*{capability_tf32_conversion_name}*
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1+| 4 | {ConvertFToTF32_token}
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*{capability_tf32_rounding_name}*
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1+| 4 | {RoundFToTF32_token}
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| '<id>' +
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'Result Type'
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| 'Result <id>'
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|========================================
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|Rev|Date|Author|Changes
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|1|2022-08-22|Dmitry Sidorov|Initial revision
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|2|2023-02-09|Dmitry Sidorov| Rename the instruction and the extension
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|========================================

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