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shuoniu-intelshuoniu-intel
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Minor updates on if constexpr statements and TODO comments
1 parent e4e9c8e commit 324ef5c

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2 files changed

+23
-30
lines changed

2 files changed

+23
-30
lines changed

‎sycl/include/sycl/ext/intel/experimental/fpga_lsu.hpp

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -64,14 +64,12 @@ template <class... _mem_access_params> class lsu final {
6464
static constexpr int32_t _target_anchor = std::get<0>(_constraint);
6565
static constexpr type _control_type = std::get<1>(_constraint);
6666
static constexpr int32_t _cycle = std::get<2>(_constraint);
67-
int32_t _type;
68-
if constexpr (_control_type == type::none) {
69-
_type = 0;
70-
} else if constexpr (_control_type == type::exact) {
67+
int32_t _type = 0; // Default: _control_type == type::none
68+
if constexpr (_control_type == type::exact) {
7169
_type = 1;
7270
} else if constexpr (_control_type == type::max) {
7371
_type = 2;
74-
} else { // _control_type == type::min
72+
} else if constexpr (_control_type == type::min) {
7573
_type = 3;
7674
}
7775

@@ -96,14 +94,12 @@ template <class... _mem_access_params> class lsu final {
9694
static constexpr int32_t _target_anchor = std::get<0>(_constraint);
9795
static constexpr type _control_type = std::get<1>(_constraint);
9896
static constexpr int32_t _cycle = std::get<2>(_constraint);
99-
int32_t _type;
100-
if constexpr (_control_type == type::none) {
101-
_type = 0;
102-
} else if constexpr (_control_type == type::exact) {
97+
int32_t _type = 0; // Default: _control_type == type::none
98+
if constexpr (_control_type == type::exact) {
10399
_type = 1;
104100
} else if constexpr (_control_type == type::max) {
105101
_type = 2;
106-
} else { // _control_type == type::min
102+
} else if constexpr (_control_type == type::min) {
107103
_type = 3;
108104
}
109105

@@ -162,6 +158,7 @@ template <class... _mem_access_params> class lsu final {
162158

163159
#if defined(__SYCL_DEVICE_ONLY__) && __has_builtin(__builtin_intel_fpga_mem)
164160
// FPGA BE will recognize this function and extract its arguments.
161+
// TODO: Pass latency control params via __builtin_intel_fpga_mem when ready.
165162
template <typename _T>
166163
static _T *__latency_control_mem_wrapper(_T *Ptr, int32_t AnchorID,
167164
int32_t TargetAnchor, int32_t Type,

‎sycl/include/sycl/ext/intel/experimental/pipes.hpp

Lines changed: 16 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -35,14 +35,12 @@ template <class _name, class _dataT, int32_t _min_capacity = 0> class pipe {
3535
static constexpr int32_t _target_anchor = std::get<0>(_constraint);
3636
static constexpr type _control_type = std::get<1>(_constraint);
3737
static constexpr int32_t _cycle = std::get<2>(_constraint);
38-
int32_t _type;
39-
if constexpr (_control_type == type::none) {
40-
_type = 0;
41-
} else if constexpr (_control_type == type::exact) {
38+
int32_t _type = 0; // Default: _control_type == type::none
39+
if constexpr (_control_type == type::exact) {
4240
_type = 1;
4341
} else if constexpr (_control_type == type::max) {
4442
_type = 2;
45-
} else { // _control_type == type::min
43+
} else if constexpr (_control_type == type::min) {
4644
_type = 3;
4745
}
4846

@@ -72,14 +70,12 @@ template <class _name, class _dataT, int32_t _min_capacity = 0> class pipe {
7270
static constexpr int32_t _target_anchor = std::get<0>(_constraint);
7371
static constexpr type _control_type = std::get<1>(_constraint);
7472
static constexpr int32_t _cycle = std::get<2>(_constraint);
75-
int32_t _type;
76-
if constexpr (_control_type == type::none) {
77-
_type = 0;
78-
} else if constexpr (_control_type == type::exact) {
73+
int32_t _type = 0; // Default: _control_type == type::none
74+
if constexpr (_control_type == type::exact) {
7975
_type = 1;
8076
} else if constexpr (_control_type == type::max) {
8177
_type = 2;
82-
} else { // _control_type == type::min
78+
} else if constexpr (_control_type == type::min) {
8379
_type = 3;
8480
}
8581

@@ -108,14 +104,12 @@ template <class _name, class _dataT, int32_t _min_capacity = 0> class pipe {
108104
static constexpr int32_t _target_anchor = std::get<0>(_constraint);
109105
static constexpr type _control_type = std::get<1>(_constraint);
110106
static constexpr int32_t _cycle = std::get<2>(_constraint);
111-
int32_t _type;
112-
if constexpr (_control_type == type::none) {
113-
_type = 0;
114-
} else if constexpr (_control_type == type::exact) {
107+
int32_t _type = 0; // Default: _control_type == type::none
108+
if constexpr (_control_type == type::exact) {
115109
_type = 1;
116110
} else if constexpr (_control_type == type::max) {
117111
_type = 2;
118-
} else { // _control_type == type::min
112+
} else if constexpr (_control_type == type::min) {
119113
_type = 3;
120114
}
121115

@@ -143,14 +137,12 @@ template <class _name, class _dataT, int32_t _min_capacity = 0> class pipe {
143137
static constexpr int32_t _target_anchor = std::get<0>(_constraint);
144138
static constexpr type _control_type = std::get<1>(_constraint);
145139
static constexpr int32_t _cycle = std::get<2>(_constraint);
146-
int32_t _type;
147-
if constexpr (_control_type == type::none) {
148-
_type = 0;
149-
} else if constexpr (_control_type == type::exact) {
140+
int32_t _type = 0; // Default: _control_type == type::none
141+
if constexpr (_control_type == type::exact) {
150142
_type = 1;
151143
} else if constexpr (_control_type == type::max) {
152144
_type = 2;
153-
} else { // _control_type == type::min
145+
} else if constexpr (_control_type == type::min) {
154146
_type = 3;
155147
}
156148

@@ -173,6 +165,7 @@ template <class _name, class _dataT, int32_t _min_capacity = 0> class pipe {
173165
m_Capacity};
174166

175167
// FPGA BE will recognize this function and extract its arguments.
168+
// TODO: Pass latency control parameters via the __spirv_* builtin when ready.
176169
template <typename _T>
177170
static int32_t
178171
__latency_control_nb_read_wrapper(__ocl_RPipeTy<_T> Pipe, _T *Data,
@@ -182,6 +175,7 @@ template <class _name, class _dataT, int32_t _min_capacity = 0> class pipe {
182175
}
183176

184177
// FPGA BE will recognize this function and extract its arguments.
178+
// TODO: Pass latency control parameters via the __spirv_* builtin when ready.
185179
template <typename _T>
186180
static int32_t
187181
__latency_control_nb_write_wrapper(__ocl_WPipeTy<_T> Pipe, const _T *Data,
@@ -191,6 +185,7 @@ template <class _name, class _dataT, int32_t _min_capacity = 0> class pipe {
191185
}
192186

193187
// FPGA BE will recognize this function and extract its arguments.
188+
// TODO: Pass latency control parameters via the __spirv_* builtin when ready.
194189
template <typename _T>
195190
static void __latency_control_bl_read_wrapper(__ocl_RPipeTy<_T> Pipe,
196191
_T *Data, int32_t AnchorID,
@@ -200,6 +195,7 @@ template <class _name, class _dataT, int32_t _min_capacity = 0> class pipe {
200195
}
201196

202197
// FPGA BE will recognize this function and extract its arguments.
198+
// TODO: Pass latency control parameters via the __spirv_* builtin when ready.
203199
template <typename _T>
204200
static void
205201
__latency_control_bl_write_wrapper(__ocl_WPipeTy<_T> Pipe, const _T *Data,

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