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dm-vodopyanovdm-vodopyanov
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Merge remote-tracking branch 'upstream/sycl' into private/dvodopya/update-oneapi-and-intel-extensions
2 parents 3fbc2d2 + a418e1c commit 424eeac

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‎CONTRIBUTING.md

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@@ -66,11 +66,6 @@ There are 3 types of tests which are used for DPC++ toolchain validation:
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should not have hardware (e.g. GPU, FPGA, etc.) or external software
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dependencies (e.g. OpenCL, Level Zero, CUDA runtimes). All tests not following
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this approach should be moved to DPC++ end-to-end or SYCL-CTS tests.
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However, the tests for a feature under active development requiring atomic
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change for tests and product can be put to
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[sycl/test/on-device](../../sycl/test/on-device) temporarily. It is developer
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responsibility to move the tests to DPC++ E2E test suite or SYCL-CTS once
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the feature is stabilized.
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**Guidelines for adding DPC++ in-tree LIT tests (DPC++ Clang FE tests)**:
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- Use `sycl::` namespace instead of `cl::sycl::`

‎clang/include/clang/Driver/Options.td

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@@ -2628,14 +2628,6 @@ def fsycl_device_code_split_EQ : Joined<["-"], "fsycl-device-code-split=">,
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def fsycl_device_code_split : Flag<["-"], "fsycl-device-code-split">, Alias<fsycl_device_code_split_EQ>,
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AliasArgs<["auto"]>, Flags<[CC1Option, CoreOption]>,
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HelpText<"Perform SYCL device code split in the 'auto' mode, i.e. use heuristic to distribute device code across modules">;
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def fsycl_device_code_split_esimd : Flag<["-"], "fsycl-device-code-split-esimd">,
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Flags<[CC1Option, CoreOption]>, HelpText<"Split SYCL and ESIMD kernels into separate modules">;
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def fno_sycl_device_code_split_esimd : Flag<["-"], "fno-sycl-device-code-split-esimd">,
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Flags<[CC1Option, CoreOption]>, HelpText<"Don't split SYCL and ESIMD kernels into separate modules">;
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def fsycl_device_code_lower_esimd : Flag<["-"], "fsycl-device-code-lower-esimd">,
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Flags<[CC1Option, CoreOption]>, HelpText<"Lower ESIMD-specific constructs">;
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def fno_sycl_device_code_lower_esimd : Flag<["-"], "fno-sycl-device-code-lower-esimd">,
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Flags<[CC1Option, CoreOption]>, HelpText<"Do not lower ESIMD-specific constructs">;
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def fsycl_instrument_device_code : Flag<["-"], "fsycl-instrument-device-code">,
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Group<sycl_Group>, Flags<[CC1Option, CoreOption]>,
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HelpText<"Add ITT instrumentation intrinsics calls">,

‎clang/lib/Driver/Driver.cpp

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@@ -2932,6 +2932,18 @@ bool Driver::checkForSYCLDefaultDevice(Compilation &C,
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if (Args.hasArg(options::OPT_fno_sycl_link_spirv))
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return false;
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// Do not do the check if the default device is passed in -fsycl-targets
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// or if -fsycl-targets isn't passed (that implies default device)
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if (const Arg *A = Args.getLastArg(options::OPT_fsycl_targets_EQ)) {
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for (const char *Val : A->getValues()) {
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llvm::Triple TT(C.getDriver().MakeSYCLDeviceTriple(Val));
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if (TT.isSPIR() && TT.getSubArch() == llvm::Triple::NoSubArch)
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// Default triple found
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return false;
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}
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} else if (!Args.hasArg(options::OPT_fintelfpga))
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return false;
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SmallVector<const char *, 16> AllArgs(getLinkerArgs(C, Args, true));
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for (StringRef Arg : AllArgs) {
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if (hasSYCLDefaultSection(C, Arg))

‎clang/lib/Driver/ToolChains/Clang.cpp

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@@ -8774,7 +8774,7 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA,
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ExtArg += ",+SPV_INTEL_usm_storage_classes";
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else
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// Don't enable several freshly added extensions on FPGA H/W
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ExtArg += ",+SPV_INTEL_token_type";
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ExtArg += ",+SPV_INTEL_token_type,+SPV_INTEL_bfloat16_conversion";
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TranslatorArgs.push_back(TCArgs.MakeArgString(ExtArg));
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}
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for (auto I : Inputs) {
@@ -8945,13 +8945,8 @@ void SYCLPostLink::ConstructJob(Compilation &C, const JobAction &JA,
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// Symbol file and specialization constant info generation is mandatory -
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// add options unconditionally
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addArgs(CmdArgs, TCArgs, {"-symbols"});
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// By default we split SYCL and ESIMD kernels into separate modules
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if (TCArgs.hasFlag(options::OPT_fsycl_device_code_split_esimd,
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options::OPT_fno_sycl_device_code_split_esimd, true))
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addArgs(CmdArgs, TCArgs, {"-split-esimd"});
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if (TCArgs.hasFlag(options::OPT_fsycl_device_code_lower_esimd,
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options::OPT_fno_sycl_device_code_lower_esimd, true))
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addArgs(CmdArgs, TCArgs, {"-lower-esimd"});
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addArgs(CmdArgs, TCArgs, {"-split-esimd"});
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addArgs(CmdArgs, TCArgs, {"-lower-esimd"});
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}
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addArgs(CmdArgs, TCArgs,
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{StringRef(getSYCLPostLinkOptimizationLevel(TCArgs))});

‎clang/test/Driver/sycl-offload-with-split.c

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@@ -299,25 +299,15 @@
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// Check ESIMD device code split.
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// RUN: %clang -### -fsycl %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT
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// RUN: %clang_cl -### -fsycl %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT
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// RUN: %clang -### -fsycl -fsycl-device-code-split-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT
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// RUN: %clang_cl -### -fsycl -fsycl-device-code-split-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT
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// RUN: %clang -### -fsycl -fno-sycl-device-code-split-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-SPLIT
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// RUN: %clang_cl -### -fsycl -fno-sycl-device-code-split-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-SPLIT
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// RUN: %clang -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT
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// RUN: %clang -### -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT
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// RUN: %clang_cl -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT
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// CHK-ESIMD-SPLIT: sycl-post-link{{.*}} "-split-esimd"
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// CHK-NO-ESIMD-SPLIT-NOT: sycl-post-link{{.*}} "-split-esimd"
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// Check lowering of ESIMD device code.
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// RUN: %clang -### -fsycl %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER
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// RUN: %clang_cl -### -fsycl %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER
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// RUN: %clang -### -fsycl -fsycl-device-code-lower-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER
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// RUN: %clang_cl -### -fsycl -fsycl-device-code-lower-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER
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// RUN: %clang -### -fsycl -fno-sycl-device-code-lower-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-LOWER
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// RUN: %clang_cl -### -fsycl -fno-sycl-device-code-lower-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-LOWER
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// RUN: %clang -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER
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// RUN: %clang -### -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER
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// RUN: %clang_cl -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER
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// CHK-ESIMD-LOWER: sycl-post-link{{.*}} "-lower-esimd"
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// CHK-NO-ESIMD-LOWER-NOT: sycl-post-link{{.*}} "-lower-esimd"

‎clang/test/Driver/sycl-offload.cpp

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@@ -96,3 +96,10 @@
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// RUN: | FileCheck -check-prefix NO_IMPLIED_DEVICE %s
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// NO_IMPLIED_DEVICE: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64-unknown-unknown-sycldevice"{{.*}} "-check-section"
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// NO_IMPLIED_DEVICE-NOT: clang-offload-bundler{{.*}} "-targets={{.*}}spir64-unknown-unknown-sycldevice{{.*}}" "-unbundle"
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/// Passing in the default triple should allow for -Xsycl-target options
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// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64 -Xsycl-target-backend=spir64 -DFOO -Xsycl-target-linker=spir64 -DFOO2 %S/Inputs/SYCL/objlin64.o 2>&1 \
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// RUN: | FileCheck -check-prefixes=SYCL_TARGET_OPT %s
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// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -Xsycl-target-backend=spir64 -DFOO -Xsycl-target-linker=spir64 -DFOO2 %S/Inputs/SYCL/objlin64.o 2>&1 \
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// RUN: | FileCheck -check-prefixes=SYCL_TARGET_OPT %s
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// SYCL_TARGET_OPT: clang-offload-wrapper{{.*}} "-compile-opts=-DFOO" "-link-opts=-DFOO2"

‎clang/test/Driver/sycl-spirv-ext.c

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@@ -50,7 +50,8 @@
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// CHECK-DEFAULT-SAME:,+SPV_INTEL_fpga_dsp_control
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// CHECK-DEFAULT-SAME:,+SPV_INTEL_arithmetic_fence
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// CHECK-DEFAULT-SAME:,+SPV_INTEL_runtime_aligned
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// CHECK-DEFAULT-SAME:,+SPV_INTEL_token_type"
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// CHECK-DEFAULT-SAME:,+SPV_INTEL_token_type
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// CHECK-DEFAULT-SAME:,+SPV_INTEL_bfloat16_conversion"
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// CHECK-FPGA-HW: llvm-spirv{{.*}}"-spirv-ext=-all
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// CHECK-FPGA-HW-SAME:,+SPV_EXT_shader_atomic_float_add
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// CHECK-FPGA-HW-SAME:,+SPV_EXT_shader_atomic_float_min_max

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