Skip to content

Commit 436576a

Browse files
nikicnikic
committed
[Attributor] Convert some tests to opaque pointers (NFC)
Check lines were regenerated for these. The alignment changes in byval-2. look suspicious at first glance, but actually only propagate pre-existing UB.
1 parent 4f57562 commit 436576a

File tree

15 files changed

+2076
-2345
lines changed

15 files changed

+2076
-2345
lines changed

‎llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll

Lines changed: 46 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -6,118 +6,112 @@
66

77
target triple = "x86_64-unknown-linux-gnu"
88

9-
define internal fastcc void @no_promote_avx2(<4 x i64>* %arg, <4 x i64>* readonly %arg1) #0 {
9+
define internal fastcc void @no_promote_avx2(ptr %arg, ptr readonly %arg1) #0 {
1010
; CHECK: Function Attrs: inlinehint nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
1111
; CHECK-LABEL: define {{[^@]+}}@no_promote_avx2
12-
; CHECK-SAME: (<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[ARG:%.*]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[ARG1:%.*]]) #[[ATTR0:[0-9]+]] {
12+
; CHECK-SAME: (ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[ARG:%.*]], ptr noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[ARG1:%.*]]) #[[ATTR0:[0-9]+]] {
1313
; CHECK-NEXT: bb:
14-
; CHECK-NEXT: [[TMP:%.*]] = load <4 x i64>, <4 x i64>* [[ARG1]], align 32
15-
; CHECK-NEXT: store <4 x i64> [[TMP]], <4 x i64>* [[ARG]], align 32
14+
; CHECK-NEXT: [[TMP:%.*]] = load <4 x i64>, ptr [[ARG1]], align 32
15+
; CHECK-NEXT: store <4 x i64> [[TMP]], ptr [[ARG]], align 32
1616
; CHECK-NEXT: ret void
1717
;
1818
bb:
19-
%tmp = load <4 x i64>, <4 x i64>* %arg1
20-
store <4 x i64> %tmp, <4 x i64>* %arg
19+
%tmp = load <4 x i64>, ptr %arg1
20+
store <4 x i64> %tmp, ptr %arg
2121
ret void
2222
}
2323

24-
define void @no_promote(<4 x i64>* %arg) #1 {
24+
define void @no_promote(ptr %arg) #1 {
2525
; TUNIT: Function Attrs: nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
2626
; TUNIT-LABEL: define {{[^@]+}}@no_promote
27-
; TUNIT-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
27+
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
2828
; TUNIT-NEXT: bb:
2929
; TUNIT-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
3030
; TUNIT-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32
31-
; TUNIT-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
32-
; TUNIT-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3:[0-9]+]]
33-
; TUNIT-NEXT: call fastcc void @no_promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) #[[ATTR4:[0-9]+]]
34-
; TUNIT-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
35-
; TUNIT-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
31+
; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3:[0-9]+]]
32+
; TUNIT-NEXT: call fastcc void @no_promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], ptr noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) #[[ATTR4:[0-9]+]]
33+
; TUNIT-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr [[TMP2]], align 32
34+
; TUNIT-NEXT: store <4 x i64> [[TMP4]], ptr [[ARG]], align 2
3635
; TUNIT-NEXT: ret void
3736
;
3837
; CGSCC: Function Attrs: nofree nosync nounwind willreturn memory(argmem: readwrite) uwtable
3938
; CGSCC-LABEL: define {{[^@]+}}@no_promote
40-
; CGSCC-SAME: (<4 x i64>* nocapture nofree noundef nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
39+
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
4140
; CGSCC-NEXT: bb:
4241
; CGSCC-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
4342
; CGSCC-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32
44-
; CGSCC-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
45-
; CGSCC-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3:[0-9]+]]
46-
; CGSCC-NEXT: call fastcc void @no_promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) #[[ATTR4:[0-9]+]]
47-
; CGSCC-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
48-
; CGSCC-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
43+
; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3:[0-9]+]]
44+
; CGSCC-NEXT: call fastcc void @no_promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], ptr noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) #[[ATTR4:[0-9]+]]
45+
; CGSCC-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr [[TMP2]], align 32
46+
; CGSCC-NEXT: store <4 x i64> [[TMP4]], ptr [[ARG]], align 2
4947
; CGSCC-NEXT: ret void
5048
;
5149
bb:
5250
%tmp = alloca <4 x i64>, align 32
5351
%tmp2 = alloca <4 x i64>, align 32
54-
%tmp3 = bitcast <4 x i64>* %tmp to i8*
55-
call void @llvm.memset.p0i8.i64(i8* align 32 %tmp3, i8 0, i64 32, i1 false)
56-
call fastcc void @no_promote_avx2(<4 x i64>* %tmp2, <4 x i64>* %tmp)
57-
%tmp4 = load <4 x i64>, <4 x i64>* %tmp2, align 32
58-
store <4 x i64> %tmp4, <4 x i64>* %arg, align 2
52+
call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)
53+
call fastcc void @no_promote_avx2(ptr %tmp2, ptr %tmp)
54+
%tmp4 = load <4 x i64>, ptr %tmp2, align 32
55+
store <4 x i64> %tmp4, ptr %arg, align 2
5956
ret void
6057
}
6158

62-
define internal fastcc void @promote_avx2(<4 x i64>* %arg, <4 x i64>* readonly %arg1) #0 {
59+
define internal fastcc void @promote_avx2(ptr %arg, ptr readonly %arg1) #0 {
6360
; CHECK: Function Attrs: inlinehint nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
6461
; CHECK-LABEL: define {{[^@]+}}@promote_avx2
65-
; CHECK-SAME: (<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[ARG:%.*]], <4 x i64> [[TMP0:%.*]]) #[[ATTR0]] {
62+
; CHECK-SAME: (ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[ARG:%.*]], <4 x i64> [[TMP0:%.*]]) #[[ATTR0]] {
6663
; CHECK-NEXT: bb:
6764
; CHECK-NEXT: [[ARG1_PRIV:%.*]] = alloca <4 x i64>, align 32
68-
; CHECK-NEXT: store <4 x i64> [[TMP0]], <4 x i64>* [[ARG1_PRIV]], align 32
69-
; CHECK-NEXT: [[TMP:%.*]] = load <4 x i64>, <4 x i64>* [[ARG1_PRIV]], align 32
70-
; CHECK-NEXT: store <4 x i64> [[TMP]], <4 x i64>* [[ARG]], align 32
65+
; CHECK-NEXT: store <4 x i64> [[TMP0]], ptr [[ARG1_PRIV]], align 32
66+
; CHECK-NEXT: [[TMP:%.*]] = load <4 x i64>, ptr [[ARG1_PRIV]], align 32
67+
; CHECK-NEXT: store <4 x i64> [[TMP]], ptr [[ARG]], align 32
7168
; CHECK-NEXT: ret void
7269
;
7370
bb:
74-
%tmp = load <4 x i64>, <4 x i64>* %arg1
75-
store <4 x i64> %tmp, <4 x i64>* %arg
71+
%tmp = load <4 x i64>, ptr %arg1
72+
store <4 x i64> %tmp, ptr %arg
7673
ret void
7774
}
7875

79-
define void @promote(<4 x i64>* %arg) #0 {
76+
define void @promote(ptr %arg) #0 {
8077
; TUNIT: Function Attrs: inlinehint nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
8178
; TUNIT-LABEL: define {{[^@]+}}@promote
82-
; TUNIT-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR0]] {
79+
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR0]] {
8380
; TUNIT-NEXT: bb:
8481
; TUNIT-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
8582
; TUNIT-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32
86-
; TUNIT-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
87-
; TUNIT-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3]]
88-
; TUNIT-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* [[TMP]], align 32
89-
; TUNIT-NEXT: call fastcc void @promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) #[[ATTR4]]
90-
; TUNIT-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
91-
; TUNIT-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
83+
; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3]]
84+
; TUNIT-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr [[TMP]], align 32
85+
; TUNIT-NEXT: call fastcc void @promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) #[[ATTR4]]
86+
; TUNIT-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr [[TMP2]], align 32
87+
; TUNIT-NEXT: store <4 x i64> [[TMP4]], ptr [[ARG]], align 2
9288
; TUNIT-NEXT: ret void
9389
;
9490
; CGSCC: Function Attrs: inlinehint nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
9591
; CGSCC-LABEL: define {{[^@]+}}@promote
96-
; CGSCC-SAME: (<4 x i64>* nocapture nofree noundef nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) #[[ATTR0]] {
92+
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) #[[ATTR0]] {
9793
; CGSCC-NEXT: bb:
9894
; CGSCC-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
9995
; CGSCC-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32
100-
; CGSCC-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
101-
; CGSCC-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3]]
102-
; CGSCC-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* [[TMP]], align 32
103-
; CGSCC-NEXT: call fastcc void @promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) #[[ATTR4]]
104-
; CGSCC-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
105-
; CGSCC-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
96+
; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3]]
97+
; CGSCC-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr [[TMP]], align 32
98+
; CGSCC-NEXT: call fastcc void @promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) #[[ATTR4]]
99+
; CGSCC-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr [[TMP2]], align 32
100+
; CGSCC-NEXT: store <4 x i64> [[TMP4]], ptr [[ARG]], align 2
106101
; CGSCC-NEXT: ret void
107102
;
108103
bb:
109104
%tmp = alloca <4 x i64>, align 32
110105
%tmp2 = alloca <4 x i64>, align 32
111-
%tmp3 = bitcast <4 x i64>* %tmp to i8*
112-
call void @llvm.memset.p0i8.i64(i8* align 32 %tmp3, i8 0, i64 32, i1 false)
113-
call fastcc void @promote_avx2(<4 x i64>* %tmp2, <4 x i64>* %tmp)
114-
%tmp4 = load <4 x i64>, <4 x i64>* %tmp2, align 32
115-
store <4 x i64> %tmp4, <4 x i64>* %arg, align 2
106+
call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)
107+
call fastcc void @promote_avx2(ptr %tmp2, ptr %tmp)
108+
%tmp4 = load <4 x i64>, ptr %tmp2, align 32
109+
store <4 x i64> %tmp4, ptr %arg, align 2
116110
ret void
117111
}
118112

119113
; Function Attrs: argmemonly nounwind
120-
declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1) #2
114+
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1) #2
121115

122116
attributes #0 = { inlinehint norecurse nounwind uwtable "target-features"="+avx2" }
123117
attributes #1 = { nounwind uwtable }

0 commit comments

Comments
 (0)