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davemgreendavemgreen
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[AArch64] Tests for implicit zero patterns. NFC
See D149616
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‎llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll

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Original file line numberDiff line numberDiff line change
@@ -32,3 +32,117 @@ entry:
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ret <8 x i8> %vtbl11.i
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}
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define <8 x i8> @tbl1v8i8(ptr nocapture noundef readonly %in, <8 x i8> noundef %idx) {
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; CHECK-LABEL: tbl1v8i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr q1, [x0]
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; CHECK-NEXT: shrn v1.8b, v1.8h, #4
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; CHECK-NEXT: tbl v0.8b, { v1.16b }, v0.8b
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; CHECK-NEXT: ret
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entry:
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%0 = load <8 x i16>, ptr %in, align 2
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%1 = lshr <8 x i16> %0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
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%vshrn_n = trunc <8 x i16> %1 to <8 x i8>
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%vtbl1.i = shufflevector <8 x i8> %vshrn_n, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %idx)
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ret <8 x i8> %vtbl11.i
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}
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define <8 x i16> @addpv4i16(<4 x i16> noundef %a, <4 x i16> noundef %b) {
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; CHECK-LABEL: addpv4i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: addp v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: mov v0.d[1], v2.d[0]
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; CHECK-NEXT: ret
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entry:
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%vpadd_v2.i = tail call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %a, <4 x i16> %b)
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%shuffle.i = shufflevector <4 x i16> %vpadd_v2.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle.i
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}
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define <8 x i16> @addv4i16(<4 x i16> noundef %a, <4 x i16> noundef %b) {
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; CHECK-LABEL: addv4i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: add v0.4h, v1.4h, v0.4h
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; CHECK-NEXT: mov v0.d[1], v2.d[0]
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; CHECK-NEXT: ret
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entry:
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%add.i = add <4 x i16> %b, %a
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%shuffle.i = shufflevector <4 x i16> %add.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle.i
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}
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define <16 x i8> @rshrn(<8 x i16> noundef %a, <4 x i16> noundef %b) {
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; CHECK-LABEL: rshrn:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rshrn v0.8b, v0.8h, #3
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; CHECK-NEXT: ret
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entry:
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%vrshrn_n1 = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %a, i32 3)
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%shuffle.i = shufflevector <8 x i8> %vrshrn_n1, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle.i
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}
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define <16 x i8> @tbl1(<16 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: tbl1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: tbl v0.8b, { v0.16b }, v1.8b
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; CHECK-NEXT: mov v0.d[1], v2.d[0]
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; CHECK-NEXT: ret
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entry:
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%vtbl11 = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b)
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%shuffle.i = shufflevector <8 x i8> %vtbl11, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle.i
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}
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define <2 x double> @fadd(double noundef %x, double noundef %y) {
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; CHECK-LABEL: fadd:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: fadd d0, d0, d1
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; CHECK-NEXT: mov v2.d[0], v0.d[0]
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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entry:
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%add = fadd double %x, %y
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%vecinit1 = insertelement <2 x double> poison, double %add, i64 0
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%vecinit2 = insertelement <2 x double> %vecinit1, double 0.0, i64 1
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ret <2 x double> %vecinit2
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}
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define <16 x i8> @bsl(<4 x i16> noundef %a, <4 x i16> noundef %c, <4 x i16> noundef %d, <4 x i16> noundef %b) {
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; CHECK-LABEL: bsl:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v3.2d, #0000000000000000
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; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: mov v0.d[1], v3.d[0]
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; CHECK-NEXT: ret
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entry:
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%vbsl3.i = and <4 x i16> %c, %a
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%0 = xor <4 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1>
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%vbsl4.i = and <4 x i16> %0, %d
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%vbsl5.i = or <4 x i16> %vbsl4.i, %vbsl3.i
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%1 = bitcast <4 x i16> %vbsl5.i to <8 x i8>
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%shuffle.i = shufflevector <8 x i8> %1, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle.i
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}
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define <16 x i8> @load(ptr %a, <8 x i8> %b) {
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; CHECK-LABEL: load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v1.2d, #0000000000000000
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-NEXT: ret
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entry:
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%vtbl11 = load <8 x i8>, ptr %a
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%shuffle.i = shufflevector <8 x i8> %vtbl11, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle.i
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}
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declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32)
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declare <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16>, <4 x i16>)

‎llvm/test/CodeGen/AArch64/peephole-insvigpr.mir

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,11 @@
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ret void
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}
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define void @fadd(double %v, double %p) {
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entry:
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ret void
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}
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attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }
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...
@@ -395,4 +400,54 @@ body: |
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RET_ReallyLR
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...
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---
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name: fadd
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr64, preferred-register: '' }
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- { id: 1, class: fpr64, preferred-register: '' }
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- { id: 2, class: fpr64, preferred-register: '' }
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- { id: 3, class: fpr128, preferred-register: '' }
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- { id: 4, class: fpr64, preferred-register: '' }
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- { id: 5, class: fpr128, preferred-register: '' }
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- { id: 6, class: fpr128, preferred-register: '' }
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- { id: 7, class: fpr128, preferred-register: '' }
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- { id: 8, class: fpr128, preferred-register: '' }
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- { id: 9, class: fpr128, preferred-register: '' }
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liveins:
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- { reg: '$d0', virtual-reg: '%0' }
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- { reg: '$d1', virtual-reg: '%1' }
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body: |
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bb.0.entry:
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liveins: $d0, $d1
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; CHECK-LABEL: name: fadd
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; CHECK: liveins: $d0, $d1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY1]], [[COPY]], implicit $fpcr
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; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[COPY2]], %subreg.dsub
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[FADDDrr]], %subreg.dsub
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; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, killed [[INSERT_SUBREG]], 0
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; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%1:fpr64 = COPY $d1
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%0:fpr64 = COPY $d0
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%2:fpr64 = nofpexcept FADDDrr %0, %1, implicit $fpcr
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%3:fpr128 = MOVIv2d_ns 0
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%4:fpr64 = COPY %3.dsub
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%6:fpr128 = IMPLICIT_DEF
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%5:fpr128 = INSERT_SUBREG %6, killed %4, %subreg.dsub
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%8:fpr128 = IMPLICIT_DEF
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%7:fpr128 = INSERT_SUBREG %8, killed %2, %subreg.dsub
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%9:fpr128 = INSvi64lane %7, 1, killed %5, 0
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$q0 = COPY %9
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RET_ReallyLR implicit $q0
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...

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