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Merge from 'main' to 'sycl-web' (6 commits)
 CONFLICT (content): Merge conflict in llvm/lib/Transforms/Scalar/SROA.cpp
2 parents 99f5b90 + 61e0822 commit 4778b7e

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24 files changed

+1048
-604
lines changed

24 files changed

+1048
-604
lines changed

‎clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -271,6 +271,8 @@ int main(int argc, const char **argv) {
271271
}
272272
}
273273
auto HeaderFilter = headerFilter();
274+
if (!HeaderFilter)
275+
return 1; // error already reported.
274276
ActionFactory Factory(HeaderFilter);
275277
return clang::tooling::ClangTool(OptionsParser->getCompilations(),
276278
OptionsParser->getSourcePathList())

‎clang/lib/CodeGen/CGCall.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -108,10 +108,12 @@ class CGCallee {
108108
SpecialKind(reinterpret_cast<uintptr_t>(functionPtr))) {
109109
AbstractInfo = abstractInfo;
110110
assert(functionPtr && "configuring callee without function pointer");
111+
#ifndef INTEL_SYCL_OPAQUEPOINTER_READY
111112
assert(functionPtr->getType()->isPointerTy());
112113
assert(functionPtr->getType()->isOpaquePointerTy() ||
113114
functionPtr->getType()->getNonOpaquePointerElementType()
114115
->isFunctionTy());
116+
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
115117
}
116118

117119
static CGCallee forBuiltin(unsigned builtinID,

‎clang/lib/Sema/SemaChecking.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4519,7 +4519,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
45194519
bool FeatureMissing = false;
45204520
SmallVector<StringRef> ReqFeatures;
45214521
StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
4522-
Features.split(ReqFeatures, ',');
4522+
Features.split(ReqFeatures, ',', -1, false);
45234523

45244524
// Check if each required feature is included
45254525
for (StringRef F : ReqFeatures) {

‎llvm/lib/Analysis/InstructionSimplify.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4888,10 +4888,15 @@ static Value *simplifyGEPInst(Type *SrcTy, Value *Ptr,
48884888
}
48894889
}
48904890

4891+
#ifdef INTEL_SYCL_OPAQUEPOINTER_READY
4892+
// All-zero GEP is a no-op, unless it performs a vector splat.
4893+
if (Ptr->getType() == GEPTy &&
4894+
#else // INTEL_SYCL_OPAQUEPOINTER_READY
48914895
// For opaque pointers an all-zero GEP is a no-op. For typed pointers,
48924896
// it may be equivalent to a bitcast.
48934897
if (Ptr->getType()->getScalarType()->isOpaquePointerTy() &&
48944898
Ptr->getType() == GEPTy &&
4899+
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
48954900
all_of(Indices, [](const auto *V) { return match(V, m_Zero()); }))
48964901
return Ptr;
48974902

‎llvm/lib/AsmParser/LLParser.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2697,7 +2697,11 @@ bool LLParser::parseType(Type *&Result, const Twine &Msg, bool AllowVoid) {
26972697
// Handle "ptr" opaque pointer type.
26982698
//
26992699
// Type ::= ptr ('addrspace' '(' uint32 ')')?
2700+
#ifdef INTEL_SYCL_OPAQUEPOINTER_READY
2701+
if (Result->isPointerTy()) {
2702+
#else // INTEL_SYCL_OPAQUEPOINTER_READY
27002703
if (Result->isOpaquePointerTy()) {
2704+
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
27012705
unsigned AddrSpace;
27022706
if (parseOptionalAddrSpace(AddrSpace))
27032707
return true;

‎llvm/lib/Bitcode/Reader/BitcodeReader.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1380,7 +1380,7 @@ unsigned BitcodeReader::getVirtualTypeID(Type *Ty,
13801380
"Incorrect cached contained type IDs");
13811381
return It->second;
13821382
}
1383-
1383+
#ifndef INTEL_SYCL_OPAQUEPOINTER_READY
13841384
#ifndef NDEBUG
13851385
if (!Ty->isOpaquePointerTy()) {
13861386
assert(Ty->getNumContainedTypes() == ChildTypeIDs.size() &&
@@ -1391,6 +1391,7 @@ unsigned BitcodeReader::getVirtualTypeID(Type *Ty,
13911391
}
13921392
}
13931393
#endif
1394+
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
13941395

13951396
unsigned TypeID = TypeList.size();
13961397
TypeList.push_back(Ty);

‎llvm/lib/FuzzMutate/Operations.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,9 +196,13 @@ OpDescriptor llvm::fuzzerop::gepDescriptor(unsigned Weight) {
196196
auto buildGEP = [](ArrayRef<Value *> Srcs, Instruction *Inst) {
197197
// TODO: It would be better to generate a random type here, rather than
198198
// generating a random value and picking its type.
199+
#ifdef INTEL_SYCL_OPAQUEPOINTER_READY
200+
Type *Ty = Srcs[1]->getType();
201+
#else // INTEL_SYCL_OPAQUEPOINTER_READY
199202
Type *Ty = Srcs[0]->getType()->isOpaquePointerTy()
200203
? Srcs[1]->getType()
201204
: Srcs[0]->getType()->getNonOpaquePointerElementType();
205+
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
202206
auto Indices = ArrayRef(Srcs).drop_front(2);
203207
return GetElementPtrInst::Create(Ty, Srcs[0], Indices, "G", Inst);
204208
};

‎llvm/lib/FuzzMutate/RandomIRBuilder.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -211,10 +211,15 @@ Value *RandomIRBuilder::newSource(BasicBlock &BB, ArrayRef<Instruction *> Insts,
211211
IP = ++I->getIterator();
212212
assert(IP != BB.end() && "guaranteed by the findPointer");
213213
}
214+
#ifdef INTEL_SYCL_OPAQUEPOINTER_READY
215+
// Pick the type independently.
216+
Type *AccessTy = RS.getSelection()->getType();
217+
#else // INTEL_SYCL_OPAQUEPOINTER_READY
214218
// For opaque pointers, pick the type independently.
215219
Type *AccessTy = Ptr->getType()->isOpaquePointerTy()
216220
? RS.getSelection()->getType()
217221
: Ptr->getType()->getNonOpaquePointerElementType();
222+
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
218223
auto *NewLoad = new LoadInst(AccessTy, Ptr, "L", &*IP);
219224

220225
// Only sample this load if it really matches the descriptor

‎llvm/lib/IR/Core.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -797,7 +797,11 @@ LLVMTypeRef LLVMPointerType(LLVMTypeRef ElementType, unsigned AddressSpace) {
797797
}
798798

799799
LLVMBool LLVMPointerTypeIsOpaque(LLVMTypeRef Ty) {
800+
#ifdef INTEL_SYCL_OPAQUEPOINTER_READY
801+
return true;
802+
#else // INTEL_SYCL_OPAQUEPOINTER_READY
800803
return unwrap(Ty)->isOpaquePointerTy();
804+
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
801805
}
802806

803807
LLVMTypeRef LLVMVectorType(LLVMTypeRef ElementType, unsigned ElementCount) {

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 63 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1150,7 +1150,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
11501150
// Jumps are expensive, compared to logic
11511151
setJumpIsExpensive();
11521152

1153-
setTargetDAGCombine({ISD::INTRINSIC_WO_CHAIN, ISD::ADD, ISD::SUB, ISD::AND,
1153+
setTargetDAGCombine({ISD::INTRINSIC_VOID, ISD::INTRINSIC_W_CHAIN,
1154+
ISD::INTRINSIC_WO_CHAIN, ISD::ADD, ISD::SUB, ISD::AND,
11541155
ISD::OR, ISD::XOR, ISD::SETCC, ISD::SELECT});
11551156
if (Subtarget.is64Bit())
11561157
setTargetDAGCombine(ISD::SRA);
@@ -10623,6 +10624,46 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
1062310624
return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
1062410625
}
1062510626

10627+
// According to the property that indexed load/store instructions
10628+
// zero-extended their indices, \p narrowIndex tries to narrow the type of index
10629+
// operand if it is matched to pattern (shl (zext x to ty), C) and bits(x) + C <
10630+
// bits(ty).
10631+
static SDValue narrowIndex(SDValue N, SelectionDAG &DAG) {
10632+
if (N.getOpcode() != ISD::SHL || !N->hasOneUse())
10633+
return SDValue();
10634+
10635+
SDValue N0 = N.getOperand(0);
10636+
if (N0.getOpcode() != ISD::ZERO_EXTEND &&
10637+
N0.getOpcode() != RISCVISD::VZEXT_VL)
10638+
return SDValue();
10639+
if (!N0->hasOneUse())
10640+
return SDValue();
10641+
10642+
APInt ShAmt;
10643+
SDValue N1 = N.getOperand(1);
10644+
if (!ISD::isConstantSplatVector(N1.getNode(), ShAmt))
10645+
return SDValue();
10646+
10647+
SDLoc DL(N);
10648+
SDValue Src = N0.getOperand(0);
10649+
EVT SrcVT = Src.getValueType();
10650+
unsigned SrcElen = SrcVT.getScalarSizeInBits();
10651+
unsigned ShAmtV = ShAmt.getZExtValue();
10652+
unsigned NewElen = PowerOf2Ceil(SrcElen + ShAmtV);
10653+
NewElen = std::max(NewElen, 8U);
10654+
10655+
// Skip if NewElen is not narrower than the original extended type.
10656+
if (NewElen >= N0.getValueType().getScalarSizeInBits())
10657+
return SDValue();
10658+
10659+
EVT NewEltVT = EVT::getIntegerVT(*DAG.getContext(), NewElen);
10660+
EVT NewVT = SrcVT.changeVectorElementType(NewEltVT);
10661+
10662+
SDValue NewExt = DAG.getNode(N0->getOpcode(), DL, NewVT, N0->ops());
10663+
SDValue NewShAmtVec = DAG.getConstant(ShAmtV, DL, NewVT);
10664+
return DAG.getNode(ISD::SHL, DL, NewVT, NewExt, NewShAmtVec);
10665+
}
10666+
1062610667
// Replace (seteq (i64 (and X, 0xffffffff)), C1) with
1062710668
// (seteq (i64 (sext_inreg (X, i32)), C1')) where C1' is C1 sign extended from
1062810669
// bit 31. Same for setne. C1' may be cheaper to materialize and the sext_inreg
@@ -12920,8 +12961,11 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1292012961
}
1292112962
break;
1292212963
}
12964+
case ISD::INTRINSIC_VOID:
12965+
case ISD::INTRINSIC_W_CHAIN:
1292312966
case ISD::INTRINSIC_WO_CHAIN: {
12924-
unsigned IntNo = N->getConstantOperandVal(0);
12967+
unsigned IntOpNo = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
12968+
unsigned IntNo = N->getConstantOperandVal(IntOpNo);
1292512969
switch (IntNo) {
1292612970
// By default we do not combine any intrinsic.
1292712971
default:
@@ -12944,6 +12988,23 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1294412988
return DAG.getConstant(-1, DL, VT);
1294512989
return DAG.getConstant(0, DL, VT);
1294612990
}
12991+
case Intrinsic::riscv_vloxei:
12992+
case Intrinsic::riscv_vloxei_mask:
12993+
case Intrinsic::riscv_vluxei:
12994+
case Intrinsic::riscv_vluxei_mask:
12995+
case Intrinsic::riscv_vsoxei:
12996+
case Intrinsic::riscv_vsoxei_mask:
12997+
case Intrinsic::riscv_vsuxei:
12998+
case Intrinsic::riscv_vsuxei_mask:
12999+
if (SDValue V = narrowIndex(N->getOperand(4), DAG)) {
13000+
SmallVector<SDValue, 8> Ops(N->ops());
13001+
Ops[4] = V;
13002+
const auto *MemSD = cast<MemIntrinsicSDNode>(N);
13003+
return DAG.getMemIntrinsicNode(N->getOpcode(), SDLoc(N), N->getVTList(),
13004+
Ops, MemSD->getMemoryVT(),
13005+
MemSD->getMemOperand());
13006+
}
13007+
return SDValue();
1294713008
}
1294813009
}
1294913010
case ISD::BITCAST: {

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 52 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -971,39 +971,57 @@ static bool findRedundantFlagInstr(MachineInstr &CmpInstr,
971971
MachineInstr **AndInstr,
972972
const TargetRegisterInfo *TRI,
973973
bool &NoSignFlag, bool &ClearsOverflowFlag) {
974-
if (CmpValDefInstr.getOpcode() != X86::SUBREG_TO_REG)
974+
if (!(CmpValDefInstr.getOpcode() == X86::SUBREG_TO_REG &&
975+
CmpInstr.getOpcode() == X86::TEST64rr) &&
976+
!(CmpValDefInstr.getOpcode() == X86::COPY &&
977+
CmpInstr.getOpcode() == X86::TEST16rr))
975978
return false;
976979

977-
if (CmpInstr.getOpcode() != X86::TEST64rr)
978-
return false;
979-
980-
// CmpInstr is a TEST64rr instruction, and `X86InstrInfo::analyzeCompare`
981-
// guarantees that it's analyzable only if two registers are identical.
982-
assert(
983-
(CmpInstr.getOperand(0).getReg() == CmpInstr.getOperand(1).getReg()) &&
984-
"CmpInstr is an analyzable TEST64rr, and `X86InstrInfo::analyzeCompare` "
985-
"requires two reg operands are the same.");
980+
// CmpInstr is a TEST16rr/TEST64rr instruction, and
981+
// `X86InstrInfo::analyzeCompare` guarantees that it's analyzable only if two
982+
// registers are identical.
983+
assert((CmpInstr.getOperand(0).getReg() == CmpInstr.getOperand(1).getReg()) &&
984+
"CmpInstr is an analyzable TEST16rr/TEST64rr, and "
985+
"`X86InstrInfo::analyzeCompare` requires two reg operands are the"
986+
"same.");
986987

987988
// Caller (`X86InstrInfo::optimizeCompareInstr`) guarantees that
988989
// `CmpValDefInstr` defines the value that's used by `CmpInstr`; in this case
989990
// if `CmpValDefInstr` sets the EFLAGS, it is likely that `CmpInstr` is
990991
// redundant.
991992
assert(
992993
(MRI->getVRegDef(CmpInstr.getOperand(0).getReg()) == &CmpValDefInstr) &&
993-
"Caller guarantees that TEST64rr is a user of SUBREG_TO_REG.");
994+
"Caller guarantees that TEST64rr is a user of SUBREG_TO_REG or TEST16rr "
995+
"is a user of COPY sub16bit.");
996+
MachineInstr *VregDefInstr = nullptr;
997+
if (CmpInstr.getOpcode() == X86::TEST16rr) {
998+
if (!CmpValDefInstr.getOperand(1).getReg().isVirtual())
999+
return false;
1000+
VregDefInstr = MRI->getVRegDef(CmpValDefInstr.getOperand(1).getReg());
1001+
if (!VregDefInstr)
1002+
return false;
1003+
// We can only remove test when AND32ri or AND64ri32 whose imm can fit 16bit
1004+
// size, others 32/64 bit ops would test higher bits which test16rr don't
1005+
// want to.
1006+
if (!((VregDefInstr->getOpcode() == X86::AND32ri ||
1007+
VregDefInstr->getOpcode() == X86::AND64ri32) &&
1008+
isUInt<16>(VregDefInstr->getOperand(2).getImm())))
1009+
return false;
1010+
}
9941011

995-
// As seen in X86 td files, CmpValDefInstr.getOperand(1).getImm() is typically
996-
// 0.
997-
if (CmpValDefInstr.getOperand(1).getImm() != 0)
998-
return false;
1012+
if (CmpInstr.getOpcode() == X86::TEST64rr) {
1013+
// As seen in X86 td files, CmpValDefInstr.getOperand(1).getImm() is
1014+
// typically 0.
1015+
if (CmpValDefInstr.getOperand(1).getImm() != 0)
1016+
return false;
9991017

1000-
// As seen in X86 td files, CmpValDefInstr.getOperand(3) is typically
1001-
// sub_32bit or sub_xmm.
1002-
if (CmpValDefInstr.getOperand(3).getImm() != X86::sub_32bit)
1003-
return false;
1018+
// As seen in X86 td files, CmpValDefInstr.getOperand(3) is typically
1019+
// sub_32bit or sub_xmm.
1020+
if (CmpValDefInstr.getOperand(3).getImm() != X86::sub_32bit)
1021+
return false;
10041022

1005-
MachineInstr *VregDefInstr =
1006-
MRI->getVRegDef(CmpValDefInstr.getOperand(2).getReg());
1023+
VregDefInstr = MRI->getVRegDef(CmpValDefInstr.getOperand(2).getReg());
1024+
}
10071025

10081026
assert(VregDefInstr && "Must have a definition (SSA)");
10091027

@@ -1021,6 +1039,11 @@ static bool findRedundantFlagInstr(MachineInstr &CmpInstr,
10211039
// ... // EFLAGS not changed
10221040
// %extended_reg = subreg_to_reg 0, %reg, %subreg.sub_32bit
10231041
// test64rr %extended_reg, %extended_reg, implicit-def $eflags
1042+
// or
1043+
// %reg = and32* ...
1044+
// ... // EFLAGS not changed.
1045+
// %src_reg = copy %reg.sub_16bit:gr32
1046+
// test16rr %src_reg, %src_reg, implicit-def $eflags
10241047
//
10251048
// If subsequent readers use a subset of bits that don't change
10261049
// after `and*` instructions, it's likely that the test64rr could
@@ -4421,10 +4444,15 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
44214444
break;
44224445
}
44234446

4424-
// Look back for the following pattern, in which case the test64rr
4425-
// instruction could be erased.
4447+
// Look back for the following pattern, in which case the
4448+
// test16rr/test64rr instruction could be erased.
44264449
//
4427-
// Example:
4450+
// Example for test16rr:
4451+
// %reg = and32ri %in_reg, 5
4452+
// ... // EFLAGS not changed.
4453+
// %src_reg = copy %reg.sub_16bit:gr32
4454+
// test16rr %src_reg, %src_reg, implicit-def $eflags
4455+
// Example for test64rr:
44284456
// %reg = and32ri %in_reg, 5
44294457
// ... // EFLAGS not changed.
44304458
// %src_reg = subreg_to_reg 0, %reg, %subreg.sub_index

‎llvm/lib/Transforms/Coroutines/Coroutines.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -596,7 +596,7 @@ static void checkAsyncFuncPointer(const Instruction *I, Value *V) {
596596
auto *AsyncFuncPtrAddr = dyn_cast<GlobalVariable>(V->stripPointerCasts());
597597
if (!AsyncFuncPtrAddr)
598598
fail(I, "llvm.coro.id.async async function pointer not a global", V);
599-
599+
#ifndef INTEL_SYCL_OPAQUEPOINTER_READY
600600
if (AsyncFuncPtrAddr->getType()->isOpaquePointerTy())
601601
return;
602602

@@ -610,6 +610,7 @@ static void checkAsyncFuncPointer(const Instruction *I, Value *V) {
610610
"llvm.coro.id.async async function pointer argument's type is not "
611611
"<{i32, i32}>",
612612
V);
613+
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
613614
}
614615

615616
void CoroIdAsyncInst::checkWellFormed() const {

‎llvm/lib/Transforms/Scalar/GVN.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -423,10 +423,16 @@ GVNPass::Expression GVNPass::ValueTable::createGEPExpr(GetElementPtrInst *GEP) {
423423
unsigned BitWidth = DL.getIndexTypeSizeInBits(PtrTy);
424424
MapVector<Value *, APInt> VariableOffsets;
425425
APInt ConstantOffset(BitWidth, 0);
426+
#ifdef INTEL_SYCL_OPAQUEPOINTER_READY
427+
if (GEP->collectOffset(DL, BitWidth, VariableOffsets, ConstantOffset)) {
428+
// Convert into offset representation, to recognize equivalent address
429+
// calculations that use different type encoding.
430+
#else // INTEL_SYCL_OPAQUEPOINTER_READY
426431
if (PtrTy->isOpaquePointerTy() &&
427432
GEP->collectOffset(DL, BitWidth, VariableOffsets, ConstantOffset)) {
428433
// For opaque pointers, convert into offset representation, to recognize
429434
// equivalent address calculations that use different type encoding.
435+
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
430436
LLVMContext &Context = GEP->getContext();
431437
E.opcode = GEP->getOpcode();
432438
E.type = nullptr;
@@ -439,8 +445,13 @@ GVNPass::Expression GVNPass::ValueTable::createGEPExpr(GetElementPtrInst *GEP) {
439445
E.varargs.push_back(
440446
lookupOrAdd(ConstantInt::get(Context, ConstantOffset)));
441447
} else {
448+
#ifdef INTEL_SYCL_OPAQUEPOINTER_READY
449+
// If converting to offset representation fails (for scalable vectors),
450+
// fall back to type-based implementation:
451+
#else // INTEL_SYCL_OPAQUEPOINTER_READY
442452
// If converting to offset representation fails (for typed pointers and
443453
// scalable vectors), fall back to type-based implementation:
454+
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
444455
E.opcode = GEP->getOpcode();
445456
E.type = GEP->getSourceElementType();
446457
for (Use &Op : GEP->operands())

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