[ARM] in ExpandTMOV32BitImm, CPSR register ops should be Defined

The CPSR registers ops of the instructions constructed in ExpandTMOV32BitImm
were marked as kill, instead of define. Best to use the pre-existing
t1CondCodeOp fn to construct CPSRs.

Reviewed By: simonwallis2

Differential Revision: https://reviews.llvm.org/D153763

Author: stuij

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

@@ -984,34 +984,34 @@ void ARMExpandPseudo::ExpandTMOV32BitImm(MachineBasicBlock &MBB,
 
   Upper8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tMOVi8), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill);
+          .add(t1CondCodeOp(true));
 
   LSL_U8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill)
+          .add(t1CondCodeOp(true))
           .addReg(DstReg)
           .addImm(8)
           .add(predOps(ARMCC::AL))
           .setMIFlags(MIFlags);
 
   Upper0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
-                 .addReg(ARM::CPSR, RegState::Kill)
+                 .add(t1CondCodeOp(true))
                  .addReg(DstReg);
 
   MachineInstr *LSL_U0_7 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
   MBB.insert(MBBI, LSL_U0_7);
 
   Lower8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill)
+          .add(t1CondCodeOp(true))
           .addReg(DstReg);
 
   MachineInstr *LSL_L8_15 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
   MBB.insert(MBBI, LSL_L8_15);
 
   Lower0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8))
                  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-                 .addReg(ARM::CPSR, RegState::Kill)
+                 .add(t1CondCodeOp(true))
                  .addReg(DstReg);
 
   Upper8_15.setMIFlags(MIFlags);

llvm/test/CodeGen/ARM/execute-only.ll

@@ -1,5 +1,3 @@
-; UNSUPPORTED: expensive_checks
-
 ; RUN: llc -mtriple=thumbv8m.base-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
 ; RUN: llc -mtriple=thumbv8m.base-eabi -mcpu=cortex-m23 -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
 ; RUN: llc -mtriple=thumbv7m-eabi      -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s