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[SYCL] Remove arbitrary upper bound for attribute argument (#3134)
Remove arbitrary upper bounds for the following attributes - SYCLIntelSchedulerTargetFmaxMhz SYCLIntelLoopFuse IntelFPGAPrivateCopies IntelFPGABankBits IntelFPGABankWidth IntelFPGANumBanks IntelFPGAMaxReplicates Signed-off-by: Elizabeth Andrews <[email protected]>
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7 files changed

+109
-142
lines changed

7 files changed

+109
-142
lines changed

‎clang/include/clang/Basic/Attr.td

Lines changed: 0 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -1282,14 +1282,6 @@ def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
12821282
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12831283
let Subjects = SubjectList<[Function], ErrorDiag>;
12841284
let Documentation = [SYCLIntelSchedulerTargetFmaxMhzAttrDocs];
1285-
let AdditionalMembers = [{
1286-
static unsigned getMinValue() {
1287-
return 0;
1288-
}
1289-
static unsigned getMaxValue() {
1290-
return 1024*1024;
1291-
}
1292-
}];
12931285
}
12941286

12951287
def SYCLIntelMaxWorkGroupSize : InheritableAttr {
@@ -1344,14 +1336,6 @@ def SYCLIntelLoopFuse : InheritableAttr {
13441336
let Accessors = [Accessor<"isIndependent",
13451337
[CXX11<"intel", "loop_fuse_independent">]>];
13461338
let Documentation = [SYCLIntelLoopFuseDocs];
1347-
let AdditionalMembers = [{
1348-
static unsigned getMinValue() {
1349-
return 0;
1350-
}
1351-
static unsigned getMaxValue() {
1352-
return 1024*1024;
1353-
}
1354-
}];
13551339
}
13561340

13571341
def C11NoReturn : InheritableAttr {
@@ -2014,14 +1998,6 @@ def IntelFPGABankWidth : Attr {
20141998
Field], ErrorDiag>;
20151999
let LangOpts = [SYCLIsDevice, SYCLIsHost];
20162000
let Documentation = [IntelFPGABankWidthAttrDocs];
2017-
let AdditionalMembers = [{
2018-
static unsigned getMinValue() {
2019-
return 1;
2020-
}
2021-
static unsigned getMaxValue() {
2022-
return 1024*1024;
2023-
}
2024-
}];
20252001
}
20262002

20272003
def IntelFPGANumBanks : Attr {
@@ -2032,14 +2008,6 @@ def IntelFPGANumBanks : Attr {
20322008
Field], ErrorDiag>;
20332009
let LangOpts = [SYCLIsDevice, SYCLIsHost];
20342010
let Documentation = [IntelFPGANumBanksAttrDocs];
2035-
let AdditionalMembers = [{
2036-
static unsigned getMinValue() {
2037-
return 1;
2038-
}
2039-
static unsigned getMaxValue() {
2040-
return 1024*1024;
2041-
}
2042-
}];
20432011
}
20442012

20452013
def IntelFPGAPrivateCopies : InheritableAttr {
@@ -2049,14 +2017,6 @@ def IntelFPGAPrivateCopies : InheritableAttr {
20492017
let LangOpts = [SYCLIsDevice, SYCLIsHost];
20502018
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
20512019
let Documentation = [IntelFPGAPrivateCopiesAttrDocs];
2052-
let AdditionalMembers = [{
2053-
static unsigned getMinValue() {
2054-
return 0;
2055-
}
2056-
static unsigned getMaxValue() {
2057-
return 1024*1024;
2058-
}
2059-
}];
20602020
}
20612021

20622022
// Two string arguments.
@@ -2078,14 +2038,6 @@ def IntelFPGAMaxReplicates : Attr {
20782038
Field], ErrorDiag>;
20792039
let LangOpts = [SYCLIsDevice, SYCLIsHost];
20802040
let Documentation = [IntelFPGAMaxReplicatesAttrDocs];
2081-
let AdditionalMembers = [{
2082-
static unsigned getMinValue() {
2083-
return 1;
2084-
}
2085-
static unsigned getMaxValue() {
2086-
return 1024*1024;
2087-
}
2088-
}];
20892041
}
20902042

20912043
def IntelFPGASimpleDualPort : Attr {
@@ -2121,14 +2073,6 @@ def IntelFPGABankBits : Attr {
21212073
Field], ErrorDiag>;
21222074
let LangOpts = [SYCLIsDevice, SYCLIsHost];
21232075
let Documentation = [IntelFPGABankBitsDocs];
2124-
let AdditionalMembers = [{
2125-
static unsigned getMinValue() {
2126-
return 0;
2127-
}
2128-
static unsigned getMaxValue() {
2129-
return 1024*1024;
2130-
}
2131-
}];
21322076
}
21332077

21342078
def IntelFPGAForcePow2Depth : Attr {

‎clang/include/clang/Sema/Sema.h

Lines changed: 35 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -10206,12 +10206,10 @@ class Sema final {
1020610206
void AddIntelFPGABankBitsAttr(Decl *D, const AttributeCommonInfo &CI,
1020710207
Expr **Exprs, unsigned Size);
1020810208
template <typename AttrType>
10209-
void addIntelSYCLSingleArgFunctionAttr(Decl *D, const AttributeCommonInfo &CI,
10210-
Expr *E);
10209+
void addIntelSingleArgAttr(Decl *D, const AttributeCommonInfo &CI, Expr *E);
1021110210
template <typename AttrType>
10212-
void addIntelSYCLTripleArgFunctionAttr(Decl *D, const AttributeCommonInfo &CI,
10213-
Expr *XDimExpr, Expr *YDimExpr,
10214-
Expr *ZDimExpr);
10211+
void addIntelTripleArgAttr(Decl *D, const AttributeCommonInfo &CI,
10212+
Expr *XDimExpr, Expr *YDimExpr, Expr *ZDimExpr);
1021510213
/// AddAlignedAttr - Adds an aligned attribute to a particular declaration.
1021610214
void AddAlignedAttr(Decl *D, const AttributeCommonInfo &CI, Expr *E,
1021710215
bool IsPackExpansion);
@@ -13059,9 +13057,8 @@ class Sema final {
1305913057
};
1306013058

1306113059
template <typename AttrType>
13062-
void Sema::addIntelSYCLSingleArgFunctionAttr(Decl *D,
13063-
const AttributeCommonInfo &CI,
13064-
Expr *E) {
13060+
void Sema::addIntelSingleArgAttr(Decl *D, const AttributeCommonInfo &CI,
13061+
Expr *E) {
1306513062
assert(E && "Attribute must have an argument.");
1306613063

1306713064
if (!E->isInstantiationDependent()) {
@@ -13072,27 +13069,42 @@ void Sema::addIntelSYCLSingleArgFunctionAttr(Decl *D,
1307213069
E = ICE.get();
1307313070
int32_t ArgInt = ArgVal.getSExtValue();
1307413071
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelNumSimdWorkItems ||
13075-
CI.getParsedKind() == ParsedAttr::AT_IntelReqdSubGroupSize) {
13072+
CI.getParsedKind() == ParsedAttr::AT_IntelReqdSubGroupSize ||
13073+
CI.getParsedKind() == ParsedAttr::AT_IntelFPGAMaxReplicates) {
1307613074
if (ArgInt <= 0) {
1307713075
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
13078-
<< CI.getAttrName() << /*positive*/ 0;
13076+
<< CI << /*positive*/ 0;
1307913077
return;
1308013078
}
1308113079
}
1308213080
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim) {
1308313081
if (ArgInt < 0) {
1308413082
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
13085-
<< CI.getAttrName() << /*non-negative*/ 1;
13083+
<< CI << /*non-negative*/ 1;
1308613084
return;
1308713085
}
1308813086
if (ArgInt > 3) {
1308913087
Diag(E->getBeginLoc(), diag::err_attribute_argument_out_of_range)
13090-
<< CI.getAttrName() << 0 << 3 << E->getSourceRange();
13088+
<< CI << 0 << 3 << E->getSourceRange();
13089+
return;
13090+
}
13091+
}
13092+
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelSchedulerTargetFmaxMhz ||
13093+
CI.getParsedKind() == ParsedAttr::AT_IntelFPGAPrivateCopies) {
13094+
if (ArgInt < 0) {
13095+
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
13096+
<< CI << /*non-negative*/ 1;
1309113097
return;
1309213098
}
1309313099
}
1309413100
}
1309513101

13102+
if (CI.getParsedKind() == ParsedAttr::AT_IntelFPGAPrivateCopies) {
13103+
if (!D->hasAttr<IntelFPGAMemoryAttr>())
13104+
D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
13105+
Context, IntelFPGAMemoryAttr::Default));
13106+
}
13107+
1309613108
D->addAttr(::new (Context) AttrType(Context, CI, E));
1309713109
}
1309813110

@@ -13128,10 +13140,9 @@ static Expr *checkMaxWorkSizeAttrExpr(Sema &S, const AttributeCommonInfo &CI,
1312813140
}
1312913141

1313013142
template <typename WorkGroupAttrType>
13131-
void Sema::addIntelSYCLTripleArgFunctionAttr(Decl *D,
13132-
const AttributeCommonInfo &CI,
13133-
Expr *XDimExpr, Expr *YDimExpr,
13134-
Expr *ZDimExpr) {
13143+
void Sema::addIntelTripleArgAttr(Decl *D, const AttributeCommonInfo &CI,
13144+
Expr *XDimExpr, Expr *YDimExpr,
13145+
Expr *ZDimExpr) {
1313513146

1313613147
assert((XDimExpr && YDimExpr && ZDimExpr) &&
1313713148
"argument has unexpected null value");
@@ -13164,13 +13175,6 @@ void Sema::AddOneConstantValueAttr(Decl *D, const AttributeCommonInfo &CI,
1316413175
return;
1316513176
E = ICE.get();
1316613177
}
13167-
13168-
if (IntelFPGAPrivateCopiesAttr::classof(&TmpAttr)) {
13169-
if (!D->hasAttr<IntelFPGAMemoryAttr>())
13170-
D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
13171-
Context, IntelFPGAMemoryAttr::Default));
13172-
}
13173-
1317413178
D->addAttr(::new (Context) AttrType(Context, CI, E));
1317513179
}
1317613180

@@ -13181,12 +13185,15 @@ void Sema::AddOneConstantPowerTwoValueAttr(Decl *D,
1318113185
AttrType TmpAttr(Context, CI, E);
1318213186

1318313187
if (!E->isValueDependent()) {
13184-
ExprResult ICE;
13185-
if (checkRangedIntegralArgument<AttrType>(E, &TmpAttr, ICE))
13188+
llvm::APSInt Value;
13189+
ExprResult ICE = VerifyIntegerConstantExpression(E, &Value);
13190+
if (ICE.isInvalid())
1318613191
return;
13187-
Expr::EvalResult Result;
13188-
E->EvaluateAsInt(Result, Context);
13189-
llvm::APSInt Value = Result.Val.getInt();
13192+
if (!Value.isStrictlyPositive()) {
13193+
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
13194+
<< CI << /*positive*/ 0;
13195+
return;
13196+
}
1319013197
if (!Value.isPowerOf2()) {
1319113198
Diag(CI.getLoc(), diag::err_attribute_argument_not_power_of_two)
1319213199
<< &TmpAttr;

‎clang/lib/Sema/SemaDeclAttr.cpp

Lines changed: 22 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -3150,8 +3150,7 @@ static void handleWorkGroupSize(Sema &S, Decl *D, const ParsedAttr &AL) {
31503150
if (!checkWorkGroupSizeValues(S, D, AL))
31513151
return;
31523152

3153-
S.addIntelSYCLTripleArgFunctionAttr<WorkGroupAttr>(D, AL, XDimExpr, YDimExpr,
3154-
ZDimExpr);
3153+
S.addIntelTripleArgAttr<WorkGroupAttr>(D, AL, XDimExpr, YDimExpr, ZDimExpr);
31553154
}
31563155

31573156
// Handles work_group_size_hint.
@@ -3193,7 +3192,7 @@ static void handleSubGroupSize(Sema &S, Decl *D, const ParsedAttr &AL) {
31933192
if (D->getAttr<IntelReqdSubGroupSizeAttr>())
31943193
S.Diag(AL.getLoc(), diag::warn_duplicate_attribute) << AL;
31953194

3196-
S.addIntelSYCLSingleArgFunctionAttr<IntelReqdSubGroupSizeAttr>(D, AL, E);
3195+
S.addIntelSingleArgAttr<IntelReqdSubGroupSizeAttr>(D, AL, E);
31973196
}
31983197

31993198
// Handles num_simd_work_items.
@@ -3208,7 +3207,7 @@ static void handleNumSimdWorkItemsAttr(Sema &S, Decl *D, const ParsedAttr &A) {
32083207

32093208
S.CheckDeprecatedSYCLAttributeSpelling(A);
32103209

3211-
S.addIntelSYCLSingleArgFunctionAttr<SYCLIntelNumSimdWorkItemsAttr>(D, A, E);
3210+
S.addIntelSingleArgAttr<SYCLIntelNumSimdWorkItemsAttr>(D, A, E);
32123211
}
32133212

32143213
// Handles use_stall_enable_clusters
@@ -3239,7 +3238,7 @@ static void handleSchedulerTargetFmaxMhzAttr(Sema &S, Decl *D,
32393238

32403239
S.CheckDeprecatedSYCLAttributeSpelling(AL);
32413240

3242-
S.AddOneConstantValueAttr<SYCLIntelSchedulerTargetFmaxMhzAttr>(D, AL, E);
3241+
S.addIntelSingleArgAttr<SYCLIntelSchedulerTargetFmaxMhzAttr>(D, AL, E);
32433242
}
32443243

32453244
// Handles max_global_work_dim.
@@ -3259,7 +3258,7 @@ static void handleMaxGlobalWorkDimAttr(Sema &S, Decl *D, const ParsedAttr &A) {
32593258

32603259
S.CheckDeprecatedSYCLAttributeSpelling(A);
32613260

3262-
S.addIntelSYCLSingleArgFunctionAttr<SYCLIntelMaxGlobalWorkDimAttr>(D, A, E);
3261+
S.addIntelSingleArgAttr<SYCLIntelMaxGlobalWorkDimAttr>(D, A, E);
32633262
}
32643263

32653264
SYCLIntelLoopFuseAttr *
@@ -3312,10 +3311,13 @@ static bool checkSYCLIntelLoopFuseArgument(Sema &S,
33123311
return true;
33133312
}
33143313

3315-
SYCLIntelLoopFuseAttr TmpAttr(S.Context, CI, E);
3316-
ExprResult ICE;
3314+
if (!ArgVal->isNonNegative()) {
3315+
S.Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
3316+
<< CI << /*non-negative*/ 1;
3317+
return true;
3318+
}
33173319

3318-
return S.checkRangedIntegralArgument<SYCLIntelLoopFuseAttr>(E, &TmpAttr, ICE);
3320+
return false;
33193321
}
33203322

33213323
void Sema::addSYCLIntelLoopFuseAttr(Decl *D, const AttributeCommonInfo &CI,
@@ -5583,7 +5585,7 @@ static void handleNoGlobalWorkOffsetAttr(Sema &S, Decl *D,
55835585
? A.getArgAsExpr(0)
55845586
: IntegerLiteral::Create(S.Context, llvm::APInt(32, 1),
55855587
S.Context.IntTy, A.getLoc());
5586-
S.addIntelSYCLSingleArgFunctionAttr<SYCLIntelNoGlobalWorkOffsetAttr>(D, A, E);
5588+
S.addIntelSingleArgAttr<SYCLIntelNoGlobalWorkOffsetAttr>(D, A, E);
55875589
}
55885590

55895591
/// Handle the [[intelfpga::doublepump]] and [[intelfpga::singlepump]] attributes.
@@ -5716,9 +5718,7 @@ static void handleOneConstantPowerTwoValueAttr(Sema &S, Decl *D,
57165718
if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, A))
57175719
return;
57185720

5719-
if (A.getKind() == ParsedAttr::AT_IntelFPGABankWidth ||
5720-
A.getKind() == ParsedAttr::AT_IntelFPGANumBanks)
5721-
S.CheckDeprecatedSYCLAttributeSpelling(A);
5721+
S.CheckDeprecatedSYCLAttributeSpelling(A);
57225722

57235723
S.AddOneConstantPowerTwoValueAttr<AttrType>(D, A, A.getArgAsExpr(0));
57245724
}
@@ -5755,8 +5755,7 @@ static void handleIntelFPGAMaxReplicatesAttr(Sema &S, Decl *D,
57555755

57565756
S.CheckDeprecatedSYCLAttributeSpelling(A);
57575757

5758-
S.AddOneConstantValueAttr<IntelFPGAMaxReplicatesAttr>(D, A,
5759-
A.getArgAsExpr(0));
5758+
S.addIntelSingleArgAttr<IntelFPGAMaxReplicatesAttr>(D, A, A.getArgAsExpr(0));
57605759
}
57615760

57625761
/// Handle the merge attribute.
@@ -5833,11 +5832,14 @@ void Sema::AddIntelFPGABankBitsAttr(Decl *D, const AttributeCommonInfo &CI,
58335832
Expr::EvalResult Result;
58345833
ListIsValueDep = ListIsValueDep || E->isValueDependent();
58355834
if (!E->isValueDependent()) {
5836-
ExprResult ICE;
5837-
if (checkRangedIntegralArgument<IntelFPGABankBitsAttr>(E, &TmpAttr, ICE))
5835+
ExprResult ICE = VerifyIntegerConstantExpression(E, &Value);
5836+
if (ICE.isInvalid())
5837+
return;
5838+
if (!Value.isNonNegative()) {
5839+
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
5840+
<< CI << /*non-negative*/ 1;
58385841
return;
5839-
if (E->EvaluateAsInt(Result, Context))
5840-
Value = Result.Val.getInt();
5842+
}
58415843
E = ICE.get();
58425844
}
58435845
Args.push_back(E);
@@ -5893,8 +5895,7 @@ static void handleIntelFPGAPrivateCopiesAttr(Sema &S, Decl *D,
58935895

58945896
S.CheckDeprecatedSYCLAttributeSpelling(A);
58955897

5896-
S.AddOneConstantValueAttr<IntelFPGAPrivateCopiesAttr>(D, A,
5897-
A.getArgAsExpr(0));
5898+
S.addIntelSingleArgAttr<IntelFPGAPrivateCopiesAttr>(D, A, A.getArgAsExpr(0));
58985899
}
58995900

59005901
static void handleIntelFPGAForcePow2DepthAttr(Sema &S, Decl *D,

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