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vmaksimovmaksimo
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Merge commit '0a67b10f2ca0d32be5d08938160422527c42e5f9' into ww07-08_oldPM
2 parents 8e21f79 + 0a67b10 commit 4addbb8

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24 files changed

+532
-250
lines changed

24 files changed

+532
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‎buildbot/dependency.py

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -50,29 +50,34 @@ def do_dependency(args):
5050
ocl_header_dir = os.path.join(args.obj_dir, "OpenCL-Headers")
5151
if not os.path.isdir(ocl_header_dir):
5252
clone_cmd = ["git", "clone", "https://github.com/KhronosGroup/OpenCL-Headers",
53-
"OpenCL-Headers", "-b", "v2020.06.16"]
53+
"OpenCL-Headers", "-b", "master"]
5454
subprocess.check_call(clone_cmd, cwd=args.obj_dir)
5555
else:
5656
fetch_cmd = ["git", "pull", "--ff", "--ff-only", "origin"]
5757
subprocess.check_call(fetch_cmd, cwd=ocl_header_dir)
5858

59-
# Workaround to unblock CI until KhronosGroup/OpenCL-ICD-Loader/pull/124
60-
# is submitted
61-
checkout_cmd = ["git", "checkout", "d1b936b72b9610626ecab8a991cec18348fba047"]
59+
# Checkout fixed version to avoid unexpected issues coming from upstream
60+
# Specific version can be uplifted as soon as such need arise
61+
checkout_cmd = ["git", "checkout", "23710f1b99186065c1768fc3098ba681adc0f253"]
6262
subprocess.check_call(checkout_cmd, cwd=ocl_header_dir)
6363

6464
# fetch and build OpenCL ICD loader
6565
icd_loader_dir = os.path.join(args.obj_dir, "OpenCL-ICD-Loader")
6666
if not os.path.isdir(icd_loader_dir):
6767
clone_cmd = ["git", "clone",
6868
"https://github.com/KhronosGroup/OpenCL-ICD-Loader",
69-
"OpenCL-ICD-Loader", "-b", "v2020.06.16"]
69+
"OpenCL-ICD-Loader", "-b", "master"]
7070

7171
subprocess.check_call(clone_cmd, cwd=args.obj_dir)
7272
else:
7373
fetch_cmd = ["git", "pull", "--ff", "--ff-only", "origin"]
7474
subprocess.check_call(fetch_cmd, cwd=icd_loader_dir)
7575

76+
# Checkout fixed version to avoid unexpected issues coming from upstream
77+
# Specific version can be uplifted as soon as such need arise
78+
checkout_cmd = ["git", "checkout", "5f8249691ec8c25775789498951f8e9eb62c201d"]
79+
subprocess.check_call(checkout_cmd, cwd=icd_loader_dir)
80+
7681
icd_build_dir = os.path.join(icd_loader_dir, "build")
7782
if os.path.isdir(icd_build_dir):
7883
shutil.rmtree(icd_build_dir)
@@ -119,4 +124,3 @@ def main():
119124
ret = main()
120125
exit_code = 0 if ret else 1
121126
sys.exit(exit_code)
122-

‎clang/include/clang/Basic/Attr.td

Lines changed: 30 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -317,10 +317,14 @@ class SubjectList<list<AttrSubject> subjects, SubjectDiag diag = WarnDiag,
317317
string CustomDiag = customDiag;
318318
}
319319

320-
class LangOpt<string name, code customCode = [{}]> {
320+
class LangOpt<string name, code customCode = [{}], bit silentlyIgnore = 0> {
321321
// The language option to test; ignored when custom code is supplied.
322322
string Name = name;
323323

324+
// If set to 1, the attribute is accepted but is silently ignored. This is
325+
// useful in multi-compilation situations like SYCL.
326+
bit SilentlyIgnore = silentlyIgnore;
327+
324328
// A custom predicate, written as an expression evaluated in a context with
325329
// "LangOpts" bound.
326330
code CustomCode = customCode;
@@ -329,9 +333,10 @@ def MicrosoftExt : LangOpt<"MicrosoftExt">;
329333
def Borland : LangOpt<"Borland">;
330334
def CUDA : LangOpt<"CUDA">;
331335
def HIP : LangOpt<"HIP">;
336+
def SYCL : LangOpt<"SYCL">;
332337
def SYCLIsDevice : LangOpt<"SYCLIsDevice">;
333-
def SYCL : LangOpt<"SYCLIsDevice">;
334338
def SYCLIsHost : LangOpt<"SYCLIsHost">;
339+
def SilentlyIgnoreSYCLIsHost : LangOpt<"SYCLIsHost", "", 1>;
335340
def SYCLExplicitSIMD : LangOpt<"SYCLExplicitSIMD">;
336341
def COnly : LangOpt<"", "!LangOpts.CPlusPlus">;
337342
def CPlusPlus : LangOpt<"CPlusPlus">;
@@ -1176,7 +1181,8 @@ def SYCLKernel : InheritableAttr {
11761181
// e.g. because the function is already vectorized. Used to mark SYCL
11771182
// explicit SIMD kernels and functions.
11781183
def SYCLSimd : InheritableAttr {
1179-
let Spellings = [GNU<"sycl_explicit_simd">];
1184+
let Spellings = [GNU<"sycl_explicit_simd">,
1185+
CXX11<"intel", "sycl_explicit_simd">];
11801186
let Subjects = SubjectList<[Function]>;
11811187
let LangOpts = [SYCLExplicitSIMD];
11821188
let Documentation = [SYCLSimdDocs];
@@ -1322,7 +1328,7 @@ def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
13221328
let Spellings = [CXX11<"intelfpga","no_global_work_offset">,
13231329
CXX11<"intel","no_global_work_offset">];
13241330
let Args = [ExprArgument<"Value", /*optional*/1>];
1325-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1331+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
13261332
let Subjects = SubjectList<[Function], ErrorDiag>;
13271333
let Documentation = [SYCLIntelNoGlobalWorkOffsetAttrDocs];
13281334
}
@@ -1331,7 +1337,7 @@ def SYCLIntelLoopFuse : InheritableAttr {
13311337
let Spellings = [CXX11<"intel", "loop_fuse">,
13321338
CXX11<"intel", "loop_fuse_independent">];
13331339
let Args = [ExprArgument<"Value", /*optional=*/ 1>];
1334-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1340+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
13351341
let Subjects = SubjectList<[Function], ErrorDiag>;
13361342
let Accessors = [Accessor<"isIndependent",
13371343
[CXX11<"intel", "loop_fuse_independent">]>];
@@ -1397,7 +1403,7 @@ def IntelReqdSubGroupSize: InheritableAttr {
13971403
let Args = [ExprArgument<"Value">];
13981404
let Subjects = SubjectList<[Function], ErrorDiag>;
13991405
let Documentation = [IntelReqdSubGroupSizeDocs];
1400-
let LangOpts = [OpenCL, SYCLIsDevice, SYCLIsHost];
1406+
let LangOpts = [OpenCL, SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
14011407
}
14021408

14031409
// This attribute is both a type attribute, and a declaration attribute (for
@@ -1843,7 +1849,7 @@ def SYCLIntelFPGAInitiationInterval : StmtAttr {
18431849
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18441850
ErrorDiag, "'for', 'while', and 'do' statements">;
18451851
let Args = [ExprArgument<"IntervalExpr">];
1846-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1852+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
18471853
let HasCustomTypeTransform = 1;
18481854
let Documentation = [SYCLIntelFPGAInitiationIntervalAttrDocs];
18491855
}
@@ -1854,7 +1860,7 @@ def SYCLIntelFPGAMaxConcurrency : StmtAttr {
18541860
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18551861
ErrorDiag, "'for', 'while', and 'do' statements">;
18561862
let Args = [ExprArgument<"NThreadsExpr">];
1857-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1863+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
18581864
let HasCustomTypeTransform = 1;
18591865
let Documentation = [SYCLIntelFPGAMaxConcurrencyAttrDocs];
18601866
}
@@ -1865,7 +1871,7 @@ def SYCLIntelFPGALoopCoalesce : StmtAttr {
18651871
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18661872
ErrorDiag, "'for', 'while', and 'do' statements">;
18671873
let Args = [ExprArgument<"NExpr">];
1868-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1874+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
18691875
let HasCustomTypeTransform = 1;
18701876
let Documentation = [SYCLIntelFPGALoopCoalesceAttrDocs];
18711877
}
@@ -1875,7 +1881,7 @@ def SYCLIntelFPGADisableLoopPipelining : StmtAttr {
18751881
CXX11<"intel","disable_loop_pipelining">];
18761882
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18771883
ErrorDiag, "'for', 'while', and 'do' statements">;
1878-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1884+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
18791885
let HasCustomTypeTransform = 1;
18801886
let Documentation = [SYCLIntelFPGADisableLoopPipeliningAttrDocs];
18811887
}
@@ -1886,7 +1892,7 @@ def SYCLIntelFPGAMaxInterleaving : StmtAttr {
18861892
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18871893
ErrorDiag, "'for', 'while', and 'do' statements">;
18881894
let Args = [ExprArgument<"NExpr">];
1889-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1895+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
18901896
let HasCustomTypeTransform = 1;
18911897
let Documentation = [SYCLIntelFPGAMaxInterleavingAttrDocs];
18921898
}
@@ -1897,7 +1903,7 @@ def SYCLIntelFPGASpeculatedIterations : StmtAttr {
18971903
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18981904
ErrorDiag, "'for', 'while', and 'do' statements">;
18991905
let Args = [ExprArgument<"NExpr">];
1900-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1906+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19011907
let HasCustomTypeTransform = 1;
19021908
let Documentation = [SYCLIntelFPGASpeculatedIterationsAttrDocs];
19031909
}
@@ -1906,7 +1912,7 @@ def SYCLIntelFPGANofusion : StmtAttr {
19061912
let Spellings = [CXX11<"intel","nofusion">];
19071913
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
19081914
ErrorDiag, "'for', 'while', and 'do' statements">;
1909-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1915+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19101916
let HasCustomTypeTransform = 1;
19111917
let Documentation = [SYCLIntelFPGANofusionAttrDocs];
19121918
}
@@ -1948,7 +1954,7 @@ def IntelFPGADoublePump : Attr {
19481954
CXX11<"intel", "doublepump">];
19491955
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19501956
Field], ErrorDiag>;
1951-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1957+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19521958
let Documentation = [IntelFPGADoublePumpAttrDocs];
19531959
}
19541960

@@ -1957,7 +1963,7 @@ def IntelFPGASinglePump : Attr {
19571963
CXX11<"intel", "singlepump">];
19581964
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19591965
Field], ErrorDiag>;
1960-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1966+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19611967
let Documentation = [IntelFPGASinglePumpAttrDocs];
19621968
}
19631969

@@ -1978,7 +1984,7 @@ def IntelFPGAMemory : Attr {
19781984
}];
19791985
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19801986
Field], ErrorDiag>;
1981-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1987+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19821988
let Documentation = [IntelFPGAMemoryAttrDocs];
19831989
}
19841990

@@ -1987,7 +1993,7 @@ def IntelFPGARegister : Attr {
19871993
CXX11<"intel", "fpga_register">];
19881994
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19891995
Field], ErrorDiag>;
1990-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1996+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19911997
let Documentation = [IntelFPGARegisterAttrDocs];
19921998
}
19931999

@@ -1998,7 +2004,7 @@ def IntelFPGABankWidth : Attr {
19982004
let Args = [ExprArgument<"Value">];
19992005
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20002006
Field], ErrorDiag>;
2001-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2007+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20022008
let Documentation = [IntelFPGABankWidthAttrDocs];
20032009
}
20042010

@@ -2008,15 +2014,15 @@ def IntelFPGANumBanks : Attr {
20082014
let Args = [ExprArgument<"Value">];
20092015
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20102016
Field], ErrorDiag>;
2011-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2017+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20122018
let Documentation = [IntelFPGANumBanksAttrDocs];
20132019
}
20142020

20152021
def IntelFPGAPrivateCopies : InheritableAttr {
20162022
let Spellings = [CXX11<"intelfpga","private_copies">,
20172023
CXX11<"intel","private_copies">];
20182024
let Args = [ExprArgument<"Value">];
2019-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2025+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20202026
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
20212027
let Documentation = [IntelFPGAPrivateCopiesAttrDocs];
20222028
}
@@ -2028,7 +2034,7 @@ def IntelFPGAMerge : Attr {
20282034
let Args = [StringArgument<"Name">, StringArgument<"Direction">];
20292035
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
20302036
Field], ErrorDiag>;
2031-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2037+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20322038
let Documentation = [IntelFPGAMergeAttrDocs];
20332039
}
20342040

@@ -2038,7 +2044,7 @@ def IntelFPGAMaxReplicates : Attr {
20382044
let Args = [ExprArgument<"Value">];
20392045
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20402046
Field], ErrorDiag>;
2041-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2047+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20422048
let Documentation = [IntelFPGAMaxReplicatesAttrDocs];
20432049
}
20442050

@@ -2047,7 +2053,7 @@ def IntelFPGASimpleDualPort : Attr {
20472053
CXX11<"intel","simple_dual_port">];
20482054
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20492055
Field], ErrorDiag>;
2050-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2056+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20512057
let Documentation = [IntelFPGASimpleDualPortAttrDocs];
20522058
}
20532059

@@ -2083,7 +2089,7 @@ def IntelFPGAForcePow2Depth : Attr {
20832089
let Args = [ExprArgument<"Value">];
20842090
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20852091
Field], ErrorDiag>;
2086-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2092+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20872093
let Documentation = [IntelFPGAForcePow2DepthAttrDocs];
20882094
let AdditionalMembers = [{
20892095
static unsigned getMinValue() {

‎clang/include/clang/Basic/AttributeCommonInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,7 @@ class AttributeCommonInfo {
167167
ParsedAttr == AT_SYCLIntelMaxGlobalWorkDim ||
168168
ParsedAttr == AT_SYCLIntelNoGlobalWorkOffset ||
169169
ParsedAttr == AT_SYCLIntelUseStallEnableClusters ||
170-
ParsedAttr == AT_SYCLIntelLoopFuse)
170+
ParsedAttr == AT_SYCLIntelLoopFuse || ParsedAttr == AT_SYCLSimd)
171171
return true;
172172

173173
return false;

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8172,7 +8172,7 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA,
81728172
TranslatorArgs.push_back("-o");
81738173
TranslatorArgs.push_back(Output.getFilename());
81748174
if (getToolChain().getTriple().isSYCLDeviceEnvironment()) {
8175-
TranslatorArgs.push_back("-spirv-max-version=1.1");
8175+
TranslatorArgs.push_back("-spirv-max-version=1.3");
81768176
TranslatorArgs.push_back("-spirv-debug-info-version=legacy");
81778177
// Prevent crash in the translator if input IR contains DIExpression
81788178
// operations which don't have mapping to OpenCL.DebugInfo.100 spec.

‎clang/lib/Driver/ToolChains/SYCL.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ const char *SYCL::Linker::constructLLVMSpirvCommand(
3939
CmdArgs.push_back("-o");
4040
CmdArgs.push_back(OutputFileName);
4141
} else {
42-
CmdArgs.push_back("-spirv-max-version=1.1");
42+
CmdArgs.push_back("-spirv-max-version=1.3");
4343
CmdArgs.push_back("-spirv-ext=+all");
4444
CmdArgs.push_back("-spirv-debug-info-version=legacy");
4545
CmdArgs.push_back("-spirv-allow-extra-diexpressions");

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