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[AArch64][GlobalISel] Camp oversize v4s64 G_FPEXT operations.
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+45
-2
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2 files changed

+45
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llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -421,8 +421,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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.legalFor(
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{{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
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.clampMaxNumElements(0, s32, 2);
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getActionDefinitionsBuilder(G_FPEXT).legalFor(
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{{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}});
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getActionDefinitionsBuilder(G_FPEXT)
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.legalFor(
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{{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
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.clampMaxNumElements(0, s64, 2);
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// Conversions
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getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -march=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
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---
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name: fpext_v4s64_v4s32
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0' }
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- { reg: '$x0' }
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frameInfo:
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maxAlignment: 1
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body: |
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bb.1:
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liveins: $q0, $x0
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; CHECK-LABEL: name: fpext_v4s64_v4s32
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; CHECK: liveins: $q0, $x0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
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; CHECK: [[FPEXT:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>)
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; CHECK: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x s32>)
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; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT]](<2 x s64>)
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; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT1]](<2 x s64>)
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; CHECK: G_STORE [[UV2]](s64), [[COPY1]](p0) :: (store 8, align 32)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C]](s64)
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; CHECK: G_STORE [[UV3]](s64), [[PTR_ADD]](p0) :: (store 8 + 8)
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64)
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; CHECK: G_STORE [[UV4]](s64), [[PTR_ADD1]](p0) :: (store 8 + 16, align 16)
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; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
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; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64)
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; CHECK: G_STORE [[UV5]](s64), [[PTR_ADD2]](p0) :: (store 8 + 24)
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; CHECK: RET_ReallyLR
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%0:_(<4 x s32>) = COPY $q0
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%1:_(p0) = COPY $x0
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%2:_(<4 x s64>) = G_FPEXT %0(<4 x s32>)
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G_STORE %2(<4 x s64>), %1(p0) :: (store 32)
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RET_ReallyLR
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...

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