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| 1 | +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| 2 | +# RUN: llc -O0 -march=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s |
| 3 | +--- |
| 4 | +name: fpext_v4s64_v4s32 |
| 5 | +tracksRegLiveness: true |
| 6 | +liveins: |
| 7 | + - { reg: '$q0' } |
| 8 | + - { reg: '$x0' } |
| 9 | +frameInfo: |
| 10 | + maxAlignment: 1 |
| 11 | +body: | |
| 12 | + bb.1: |
| 13 | + liveins: $q0, $x0 |
| 14 | +
|
| 15 | + ; CHECK-LABEL: name: fpext_v4s64_v4s32 |
| 16 | + ; CHECK: liveins: $q0, $x0 |
| 17 | + ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 |
| 18 | + ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0 |
| 19 | + ; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY]](<4 x s32>) |
| 20 | + ; CHECK: [[FPEXT:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>) |
| 21 | + ; CHECK: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x s32>) |
| 22 | + ; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT]](<2 x s64>) |
| 23 | + ; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT1]](<2 x s64>) |
| 24 | + ; CHECK: G_STORE [[UV2]](s64), [[COPY1]](p0) :: (store 8, align 32) |
| 25 | + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 |
| 26 | + ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C]](s64) |
| 27 | + ; CHECK: G_STORE [[UV3]](s64), [[PTR_ADD]](p0) :: (store 8 + 8) |
| 28 | + ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 |
| 29 | + ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64) |
| 30 | + ; CHECK: G_STORE [[UV4]](s64), [[PTR_ADD1]](p0) :: (store 8 + 16, align 16) |
| 31 | + ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 |
| 32 | + ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64) |
| 33 | + ; CHECK: G_STORE [[UV5]](s64), [[PTR_ADD2]](p0) :: (store 8 + 24) |
| 34 | + ; CHECK: RET_ReallyLR |
| 35 | + %0:_(<4 x s32>) = COPY $q0 |
| 36 | + %1:_(p0) = COPY $x0 |
| 37 | + %2:_(<4 x s64>) = G_FPEXT %0(<4 x s32>) |
| 38 | + G_STORE %2(<4 x s64>), %1(p0) :: (store 32) |
| 39 | + RET_ReallyLR |
| 40 | +
|
| 41 | +... |
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