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AaronBallmanAaronBallman
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Slight redesign of the feature.
We still want to list explicitly that the attribute is accepted in host mode, otherwise there's no good way to see that the attribute is silently being accepted there. This complicates the tablegen slightly, but also makes for a more obvious feature.
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4 files changed

+35
-49
lines changed

4 files changed

+35
-49
lines changed

‎clang/include/clang/Basic/Attr.td

Lines changed: 22 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -317,11 +317,12 @@ class SubjectList<list<AttrSubject> subjects, SubjectDiag diag = WarnDiag,
317317
string CustomDiag = customDiag;
318318
}
319319

320-
class LangOpt<string name, bit warn = 1, code customCode = [{}]> {
320+
class LangOpt<string name, code customCode = [{}], bit warn = 1> {
321321
// The language option to test; ignored when custom code is supplied.
322322
string Name = name;
323323

324-
// If set to 1, diagnose the attribute as being ignored if the test fails.
324+
// If set to 0, the attribute is accepted but is silently ignored. This is
325+
// useful in multi-compilation situations like SYCL.
325326
bit Warn = warn;
326327

327328
// A custom predicate, written as an expression evaluated in a context with
@@ -333,18 +334,19 @@ def Borland : LangOpt<"Borland">;
333334
def CUDA : LangOpt<"CUDA">;
334335
def HIP : LangOpt<"HIP">;
335336
def SYCL : LangOpt<"SYCL">;
336-
def SYCLIsDevice : LangOpt<"", 0, "(LangOpts.SYCL && LangOpts.SYCLIsDevice)">;
337-
def SYCLIsHost : LangOpt<"", 0, "(LangOpts.SYCL && LangOpts.SYCLIsHost)">;
337+
def SYCLIsDevice : LangOpt<"SYCLIsDevice">;
338+
def SYCLIsHost : LangOpt<"SYCLIsHost">;
339+
def SilentlyIgnoreSYCLIsHost : LangOpt<"SYCLIsHost", "", 0>;
338340
def SYCLExplicitSIMD : LangOpt<"SYCLExplicitSIMD">;
339-
def COnly : LangOpt<"", 1, "!LangOpts.CPlusPlus">;
341+
def COnly : LangOpt<"", "!LangOpts.CPlusPlus">;
340342
def CPlusPlus : LangOpt<"CPlusPlus">;
341343
def OpenCL : LangOpt<"OpenCL">;
342344
def RenderScript : LangOpt<"RenderScript">;
343345
def ObjC : LangOpt<"ObjC">;
344346
def BlocksSupported : LangOpt<"Blocks">;
345347
def ObjCAutoRefCount : LangOpt<"ObjCAutoRefCount">;
346348
def ObjCNonFragileRuntime
347-
: LangOpt<"", 1, "LangOpts.ObjCRuntime.allowsClassStubs()">;
349+
: LangOpt<"", "LangOpts.ObjCRuntime.allowsClassStubs()">;
348350

349351
// Language option for CMSE extensions
350352
def Cmse : LangOpt<"Cmse">;
@@ -1325,7 +1327,7 @@ def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
13251327
let Spellings = [CXX11<"intelfpga","no_global_work_offset">,
13261328
CXX11<"intel","no_global_work_offset">];
13271329
let Args = [ExprArgument<"Value", /*optional*/1>];
1328-
let LangOpts = [SYCLIsDevice];
1330+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
13291331
let Subjects = SubjectList<[Function], ErrorDiag>;
13301332
let Documentation = [SYCLIntelNoGlobalWorkOffsetAttrDocs];
13311333
}
@@ -1334,7 +1336,7 @@ def SYCLIntelLoopFuse : InheritableAttr {
13341336
let Spellings = [CXX11<"intel", "loop_fuse">,
13351337
CXX11<"intel", "loop_fuse_independent">];
13361338
let Args = [ExprArgument<"Value", /*optional=*/ 1>];
1337-
let LangOpts = [SYCLIsDevice];
1339+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
13381340
let Subjects = SubjectList<[Function], ErrorDiag>;
13391341
let Accessors = [Accessor<"isIndependent",
13401342
[CXX11<"intel", "loop_fuse_independent">]>];
@@ -1398,7 +1400,7 @@ def IntelReqdSubGroupSize: InheritableAttr {
13981400
let Args = [ExprArgument<"Value">];
13991401
let Subjects = SubjectList<[Function, CXXMethod], ErrorDiag>;
14001402
let Documentation = [IntelReqdSubGroupSizeDocs];
1401-
let LangOpts = [OpenCL, SYCLIsDevice, SYCLIsHost];
1403+
let LangOpts = [OpenCL, SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
14021404
}
14031405

14041406
// This attribute is both a type attribute, and a declaration attribute (for
@@ -1949,7 +1951,7 @@ def IntelFPGADoublePump : Attr {
19491951
CXX11<"intel", "doublepump">];
19501952
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19511953
Field], ErrorDiag>;
1952-
let LangOpts = [SYCLIsDevice];
1954+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19531955
let Documentation = [IntelFPGADoublePumpAttrDocs];
19541956
}
19551957

@@ -1958,7 +1960,7 @@ def IntelFPGASinglePump : Attr {
19581960
CXX11<"intel", "singlepump">];
19591961
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19601962
Field], ErrorDiag>;
1961-
let LangOpts = [SYCLIsDevice];
1963+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19621964
let Documentation = [IntelFPGASinglePumpAttrDocs];
19631965
}
19641966

@@ -1979,7 +1981,7 @@ def IntelFPGAMemory : Attr {
19791981
}];
19801982
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19811983
Field], ErrorDiag>;
1982-
let LangOpts = [SYCLIsDevice];
1984+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19831985
let Documentation = [IntelFPGAMemoryAttrDocs];
19841986
}
19851987

@@ -1988,7 +1990,7 @@ def IntelFPGARegister : Attr {
19881990
CXX11<"intel", "fpga_register">];
19891991
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19901992
Field], ErrorDiag>;
1991-
let LangOpts = [SYCLIsDevice];
1993+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19921994
let Documentation = [IntelFPGARegisterAttrDocs];
19931995
}
19941996

@@ -1999,7 +2001,7 @@ def IntelFPGABankWidth : Attr {
19992001
let Args = [ExprArgument<"Value">];
20002002
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20012003
Field], ErrorDiag>;
2002-
let LangOpts = [SYCLIsDevice];
2004+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20032005
let Documentation = [IntelFPGABankWidthAttrDocs];
20042006
}
20052007

@@ -2009,15 +2011,15 @@ def IntelFPGANumBanks : Attr {
20092011
let Args = [ExprArgument<"Value">];
20102012
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20112013
Field], ErrorDiag>;
2012-
let LangOpts = [SYCLIsDevice];
2014+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20132015
let Documentation = [IntelFPGANumBanksAttrDocs];
20142016
}
20152017

20162018
def IntelFPGAPrivateCopies : InheritableAttr {
20172019
let Spellings = [CXX11<"intelfpga","private_copies">,
20182020
CXX11<"intel","private_copies">];
20192021
let Args = [ExprArgument<"Value">];
2020-
let LangOpts = [SYCLIsDevice];
2022+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20212023
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
20222024
let Documentation = [IntelFPGAPrivateCopiesAttrDocs];
20232025
}
@@ -2029,7 +2031,7 @@ def IntelFPGAMerge : Attr {
20292031
let Args = [StringArgument<"Name">, StringArgument<"Direction">];
20302032
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
20312033
Field], ErrorDiag>;
2032-
let LangOpts = [SYCLIsDevice];
2034+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20332035
let Documentation = [IntelFPGAMergeAttrDocs];
20342036
}
20352037

@@ -2039,7 +2041,7 @@ def IntelFPGAMaxReplicates : Attr {
20392041
let Args = [ExprArgument<"Value">];
20402042
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20412043
Field], ErrorDiag>;
2042-
let LangOpts = [SYCLIsDevice];
2044+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20432045
let Documentation = [IntelFPGAMaxReplicatesAttrDocs];
20442046
}
20452047

@@ -2048,7 +2050,7 @@ def IntelFPGASimpleDualPort : Attr {
20482050
CXX11<"intel","simple_dual_port">];
20492051
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20502052
Field], ErrorDiag>;
2051-
let LangOpts = [SYCLIsDevice];
2053+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20522054
let Documentation = [IntelFPGASimpleDualPortAttrDocs];
20532055
}
20542056

@@ -2084,7 +2086,7 @@ def IntelFPGAForcePow2Depth : Attr {
20842086
let Args = [ExprArgument<"Value">];
20852087
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20862088
Field], ErrorDiag>;
2087-
let LangOpts = [SYCLIsDevice];
2089+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20882090
let Documentation = [IntelFPGAForcePow2DepthAttrDocs];
20892091
let AdditionalMembers = [{
20902092
static unsigned getMinValue() {

‎clang/lib/Sema/SemaDeclAttr.cpp

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3211,14 +3211,6 @@ static void handleWorkGroupSizeHint(Sema &S, Decl *D, const ParsedAttr &AL) {
32113211

32123212
// Handles intel_reqd_sub_group_size.
32133213
static void handleSubGroupSize(Sema &S, Decl *D, const ParsedAttr &AL) {
3214-
// In SYCLIsHost mode, we want to ignore the attribute. In OpenCL or
3215-
// SYCLIsDevice mode, we want to process the attribute as normal. This cannot
3216-
// be handled in Attr.td unless ClangAttrEmitter.cpp gets smarter logic about
3217-
// when to suppress the "ignored attribute" warnings with a list of language
3218-
// options.
3219-
if (!S.LangOpts.SYCLIsDevice && !S.LangOpts.OpenCL)
3220-
return;
3221-
32223214
Expr *E = AL.getArgAsExpr(0);
32233215

32243216
if (D->getAttr<IntelReqdSubGroupSizeAttr>())

‎clang/test/CodeGenSYCL/loop_fusion_host.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
// RUN: %clang_cc1 -fsycl -fsycl-is-host -triple -x86_64-unknown-linux-gnu -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s
2-
// RUN: %clang_cc1 -fsycl -fsycl-is-host -triple -x86_64-unknown-linux-gnu -disable-llvm-passes -verify -Wno-sycl-2017-compat -DDIAG %s
32

43
template <typename name, typename Func>
54
__attribute__((sycl_kernel)) void kernel(const Func &kernelFunc) {
@@ -30,8 +29,3 @@ void foo() {
3029
kernel<class kernel_name_1>(f5);
3130
}
3231
// CHECK-NOT: !loop_fuse
33-
34-
#if defined(DIAG)
35-
int baz();
36-
[[intel::loop_fuse(baz())]] void func3(); // expected-error{{'loop_fuse' attribute requires an integer constant}}
37-
#endif

‎clang/utils/TableGen/ClangAttrEmitter.cpp

Lines changed: 13 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1993,18 +1993,17 @@ bool PragmaClangAttributeSupport::isAttributedSupported(
19931993
}
19941994

19951995
static std::string GenerateTestExpression(ArrayRef<Record *> LangOpts,
1996-
bool *ShouldDiagnose = nullptr) {
1996+
bool IsAttrAccepted) {
19971997
std::string Test;
19981998

19991999
for (auto *E : LangOpts) {
2000+
bool LangOptWantsWarning = E->getValueAsBit("Warn");
2001+
if (LangOptWantsWarning != IsAttrAccepted)
2002+
continue;
2003+
20002004
if (!Test.empty())
20012005
Test += " || ";
20022006

2003-
// If any of the language options say "warn", then warn if any of the
2004-
// options fail.
2005-
if (ShouldDiagnose && E->getValueAsBit("Warn"))
2006-
*ShouldDiagnose = true;
2007-
20082007
const StringRef Code = E->getValueAsString("CustomCode");
20092008
if (!Code.empty()) {
20102009
Test += "(";
@@ -2016,6 +2015,8 @@ static std::string GenerateTestExpression(ArrayRef<Record *> LangOpts,
20162015
"non-empty 'Name' field ignored because 'CustomCode' was supplied");
20172016
}
20182017
} else {
2018+
if (!IsAttrAccepted && !LangOptWantsWarning)
2019+
Test += "!";
20192020
Test += "LangOpts.";
20202021
Test += E->getValueAsString("Name");
20212022
}
@@ -2049,7 +2050,7 @@ PragmaClangAttributeSupport::generateStrictConformsTo(const Record &Attr,
20492050
// rules if the specific language options are specified.
20502051
std::vector<Record *> LangOpts = Rule.getLangOpts();
20512052
OS << " MatchRules.push_back(std::make_pair(" << Rule.getEnumValue()
2052-
<< ", /*IsSupported=*/" << GenerateTestExpression(LangOpts)
2053+
<< ", /*IsSupported=*/" << GenerateTestExpression(LangOpts, true)
20532054
<< "));\n";
20542055
}
20552056
}
@@ -3641,16 +3642,13 @@ static void GenerateLangOptRequirements(const Record &R,
36413642
if (LangOpts.empty())
36423643
return;
36433644

3644-
OS << "bool diagLangOpts(Sema &S, const ParsedAttr &Attr) ";
3645+
OS << "bool diagLangOpts(Sema &S, const ParsedAttr &PA) ";
36453646
OS << "const override {\n";
3646-
OS << " auto &LangOpts = S.LangOpts;\n";
3647-
bool Warn = false;
3648-
OS << " if (" << GenerateTestExpression(LangOpts, &Warn) << ")\n";
3647+
OS << " const auto &LangOpts = S.LangOpts;\n";
3648+
OS << " if (" << GenerateTestExpression(LangOpts, true) << ")\n";
36493649
OS << " return true;\n\n";
3650-
if (Warn) {
3651-
OS << " S.Diag(Attr.getLoc(), diag::warn_attribute_ignored) ";
3652-
OS << "<< Attr;\n";
3653-
}
3650+
OS << " if (" << GenerateTestExpression(LangOpts, false) << ")\n";
3651+
OS << " S.Diag(PA.getLoc(), diag::warn_attribute_ignored) << PA;\n";
36543652
OS << " return false;\n";
36553653
OS << "}\n\n";
36563654
}

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