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Reword to be PVC specific
It turns out that ATS-M does not support this type of partitioning, so reword the overview to note that PVC is the only supported device.
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sycl/doc/extensions/proposed/sycl_ext_intel_cslice.asciidoc

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@@ -55,11 +55,11 @@ not rely on APIs defined in this specification.*
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:multi-CCS: https://github.com/intel/compute-runtime/blob/master/level_zero/doc/experimental_extensions/MULTI_CCS_MODES.md
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Some Intel GPU devices can be partitioned at a granularity of "cslice" (compute
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slice), which is a smaller granularity than "tile". At present, the GPU device
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drivers don't expose this mode by default, so this form of partitioning is
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considered an advanced feature which most applications are not expected to use.
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This extension provides a way for these advanced applications to partition a
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device by cslice when it is enabled in the device driver.
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slice), which is a smaller granularity than "tile". This form of partitioning
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is not currently enabled by default, so it is considered an advanced feature
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which most applications are not expected to use. This extension provides a way
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for these advanced applications to partition a device by cslice when it is
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enabled in the device driver.
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Unlike "tile" partitions, a cslice partition does not have any different cache
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affinity from its sibling cslice partitions. Therefore, this extension does
@@ -68,14 +68,19 @@ not expose this type of partitioning through
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new partitioning type
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`info::partition_property::ext_intel_partition_by_cslice`.
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Intel GPU devices that support this type of partitioning currently support it
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only at the "tile" level. Therefore, a device with multiple tiles (e.g. PVC)
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must first be partitioned into per-tile sub-devices via
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`partition_by_affinity_domain`, and then each of the
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resulting sub-devices can be further partitioned by
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`ext_intel_partition_by_cslice`. Single-tile devices (e.g. ATS-M) can be
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directly partitioned by `ext_intel_partition_by_cslice` (for those ATS-M parts
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that have multiple cslice partitions).
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The only Intel GPU device that currently supports this type of partitioning is
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PVC, and this support is only available when the device driver is configured in
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{multi-CCS}[multi-CCS] mode. See that documentation for instructions on how to
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enable this mode and for other important information. Currently, it is only
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possible to partition a device by cslice if the driver is in "2 CCS Mode" or
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"4 CCS Mode". When in 2 CCS Mode, a tile can be partitioned into two cslice
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sub-devices. When in 4 CCS Mode, a tile can be partitioned into four cslice
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sub-devices.
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This type of partitioning is currently supported only at the "tile" level.
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Therefore, a device must first be partitioned into per-tile sub-devices via
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`partition_by_affinity_domain`, and then each of the resulting sub-devices can
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be further partitioned by `ext_intel_partition_by_cslice`.
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It is important to understand that the device driver virtualizes work
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submission to the cslice sub-devices. This virtualization happens only between
@@ -92,13 +97,6 @@ kernels submitted from the second process. In this second case, the device
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driver binds the process's requested cslice to a physical cslice according to
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the overall system load.
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For information about configuring the device driver to support cslice
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partitioning, see the driver documentation on {multi-CCS}[multi-CCS] mode.
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Currently, it is only possible to partition a device by cslice if the driver is
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in "2 CCS Mode" or "4 CCS Mode". When in 2 CCS Mode, a tile can be partitioned
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into two cslice sub-devices. When in 4 CCS Mode, a tile can be partitioned
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into four cslice sub-devices.
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Note that this extension can be supported by any backend and any device. If a
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backend or device does not support the concept of cslice partitions, it can
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still conform to this extension by declaring the new enumerator and member

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