Fix Clang-format issues

Signed-off-by: Soumi Manna <[email protected]>

Author: smanna12

clang/lib/Sema/SemaStmtAttr.cpp

@@ -103,21 +103,21 @@ static Attr *handleIntelFPGALoopAttr(Sema &S, const ParsedAttr &A) {
   } else if (A.getKind() == ParsedAttr::AT_SYCLIntelFPGAMaxConcurrency &&
              A.getAttributeSpellingListIndex() ==
                  SYCLIntelFPGAMaxConcurrencyAttr::
-		      CXX11_intelfpga_max_concurrency) {
+                     CXX11_intelfpga_max_concurrency) {
     S.Diag(A.getLoc(), diag::warn_attribute_spelling_deprecated) << A;
     S.Diag(A.getLoc(), diag::note_spelling_suggestion)
         << "'INTEL::max_concurrency'";
   } else if (A.getKind() == ParsedAttr::AT_SYCLIntelFPGAMaxInterleaving &&
              A.getAttributeSpellingListIndex() ==
                  SYCLIntelFPGAMaxInterleavingAttr::
-		      CXX11_intelfpga_max_interleaving) {
+                     CXX11_intelfpga_max_interleaving) {
     S.Diag(A.getLoc(), diag::warn_attribute_spelling_deprecated) << A;
     S.Diag(A.getLoc(), diag::note_spelling_suggestion)
         << "'INTEL::max_interleaving'";
   } else if (A.getKind() == ParsedAttr::AT_SYCLIntelFPGASpeculatedIterations &&
              A.getAttributeSpellingListIndex() ==
                  SYCLIntelFPGASpeculatedIterationsAttr::
-		      CXX11_intelfpga_speculated_iterations) {
+                     CXX11_intelfpga_speculated_iterations) {
     S.Diag(A.getLoc(), diag::warn_attribute_spelling_deprecated) << A;
     S.Diag(A.getLoc(), diag::note_spelling_suggestion)
         << "'INTEL::speculated_iterations'";

clang/test/CodeGenSYCL/intel-fpga-ivdep-embedded-loops.cpp

@@ -125,7 +125,7 @@ void ivdep_embedded_multiple_dimensions() {
       a[j] += j;
       [[INTEL::ivdep]] for (int k = 0; k != 10; ++k) {
         // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_DIM_3_MUL_DIMS:[0-9]+]]
-+        a[k] += k;
+         a[k] += k;
         // CHECK: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_LOOP_DIM_3_MUL_DIMS:[0-9]+]]
       }
       // CHECK: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_LOOP_DIM_2_MUL_DIMS:[0-9]+]]

clang/test/SemaSYCL/intel-fpga-local.cpp

@@ -97,7 +97,7 @@ void check_ast()
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}16
   //CHECK-NEXT: IntegerLiteral{{.*}}16{{$}}
-  [[INTEL::bank_bits(2, 3), INTEL::bankwidth(16)]]  unsigned int bank_bits_width[64];
+  [[INTEL::bank_bits(2, 3), INTEL::bankwidth(16)]] unsigned int bank_bits_width[64];
 
   //CHECK: VarDecl{{.*}}doublepump_mlab
   //CHECK: IntelFPGADoublePumpAttr

clang/test/SemaSYCL/intel-fpga-loops.cpp

@@ -43,7 +43,7 @@ void foo_deprecated() {
   // expected-warning@+2 {{attribute 'max_concurrency' is deprecated}}
   // expected-note@+1 {{did you mean to use 'INTEL::max_concurrency' instead?}}
   [[intelfpga::max_concurrency(4)]] for (int i = 0; i != 10; ++i)
-    a[i] = 0;
+      a[i] = 0;
 
   // expected-warning@+2 {{attribute 'max_interleaving' is deprecated}}
   // expected-note@+1 {{did you mean to use 'INTEL::max_interleaving' instead?}}