Merge remote-tracking branch 'intel_llvm/sycl' into public_vklochkov_reduction_N_vars_perf

Author: v-klochkov

.github/workflows/linux_post_commit.yml

@@ -29,10 +29,10 @@ jobs:
                  wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | sudo apt-key add -
                  sudo add-apt-repository "deb http://apt.llvm.org/bionic/   llvm-toolchain-bionic main"
                  sudo apt-get update
-                 sudo apt-get install -y clang-12
+                 sudo apt-get install -y clang-13
                  export ARGS="--shared-libs"
-                 export CC="clang-12"
-                 export CXX="clang++-12"
+                 export CC="clang-13"
+                 export CXX="clang++-13"
                  ;;
              NoAssertions)
                  export ARGS="--no-assertions"

CONTRIBUTING.md

@@ -54,6 +54,63 @@ see [ABI Policy Guide](sycl/doc/ABIPolicyGuide.md) for more information.
 - Run regression tests -
 [instructions](sycl/doc/GetStartedGuide.md#test-dpc-toolchain).
 
+### Tests development
+
+Every product change should be accompanied with corresponding test modification
+(adding new test(s), extending, removing or modifying existing test(s)).
+
+There are 3 types of tests which are used for DPC++ toolchain validation:
+* DPC++ in-tree LIT tests including [check-llvm](../../llvm/test),
+[check-clang](../../clang/test), [check-llvm-spirv](../../llvm-spirv/test) and
+[check-sycl](../../sycl/test) targets stored in this repository. These tests
+should not have hardware (e.g. GPU, FPGA, etc.) or external software
+dependencies (e.g. OpenCL, Level Zero, CUDA runtimes). All tests not following
+this approach should be moved to DPC++ end-to-end or SYCL-CTS tests.
+However, the tests for a feature under active development requiring atomic
+change for tests and product can be put to
+[sycl/test/on-device](../../sycl/test/on-device) temporarily. It is developer
+responsibility to move the tests to DPC++ E2E test suite or SYCL-CTS once
+the feature is stabilized.
+
+    **Guidelines for adding DPC++ in-tree LIT tests (DPC++ Clang FE tests)**:
+    - Use `sycl::` namespace instead of `cl::sycl::`
+
+    - Include sycl mock headers as system headers.
+    Example: `-internal-isystem %S/Inputs`
+    `#include "sycl.hpp"`
+
+    - Use SYCL functions for invoking kernels from the mock header `(single_task, parallel_for, parallel_for_work_group)`
+    Example:
+    ```bash
+    `#include "Inputs/sycl.hpp"`
+    sycl::queue q;
+    q.submit([&](cl::sycl::handler &h) {
+    h.single_task( { //code });
+    });
+    ```
+
+    - Add a helpful comment describing what the test does at the beginning and other comments throughout the test as necessary.
+
+    - Try to follow descriptive naming convention for variables, functions as much as possible.
+    Please refer [LLVM naming convention](https://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly)
+
+* DPC++ end-to-end (E2E) tests which are extension to
+[LLVM\* test suite](https://github.com/intel/llvm-test-suite/tree/intel/SYCL).
+A test which requires full stack including backend runtimes (e.g. OpenCL,
+Level Zero or CUDA) should be put to DPC++ E2E test suite following
+[CONTRIBUTING](https://github.com/intel/llvm-test-suite/blob/intel/CONTRIBUTING.md).
+
+* SYCL-CTS are official 
+[Khronos\* SYCL\* conformance tests](https://github.com/KhronosGroup/SYCL-CTS).
+They verify SYCL specification compatibility. All implementation details or
+extensions are out of scope for the tests. If SYCL specification has changed
+(SYCL CTS tests conflict with recent version of SYCL specification) or change
+is required in the way the tests are built with DPC++ compiler (defined in
+[FindIntel_SYCL](https://github.com/KhronosGroup/SYCL-CTS/blob/SYCL-1.2.1/master/cmake/FindIntel_SYCL.cmake))
+pull request should be created under
+[KhronosGroup/SYCL-CTS](https://github.com/KhronosGroup/SYCL-CTS) with required
+patch.
+
 ### Commit message
 
 - When writing your commit message, please make sure to follow

buildbot/dependency.conf

@@ -4,11 +4,11 @@ ocl_cpu_rt_ver=2020.11.11.0.04
 # https://github.com/intel/llvm/releases/download/2020-WW45/win-oclcpuexp-2020.11.11.0.04_rel.zip
 ocl_cpu_rt_ver_win=2020.11.11.0.04
 # Same GPU driver supports Level Zero and OpenCL
-# https://github.com/intel/compute-runtime/releases/tag/21.03.18857
-ocl_gpu_rt_ver=21.03.18857
+# https://github.com/intel/compute-runtime/releases/tag/21.04.18912
+ocl_gpu_rt_ver=21.04.18912
 # Same GPU driver supports Level Zero and OpenCL
-# https://downloadmirror.intel.com/30066/a08/igfx_win10_100.9030.zip
-ocl_gpu_rt_ver_win=27.20.100.9030
+# https://downloadmirror.intel.com/30148/a08/igfx_win10_100.9168.zip
+ocl_gpu_rt_ver_win=27.20.100.9168
 intel_sycl_ver=build
 
 # TBB binaries can be built from sources following instructions under
@@ -25,13 +25,13 @@ ocl_fpga_emu_ver=2020.11.11.0.04
 ocl_fpga_emu_ver_win=2020.11.11.0.04
 fpga_ver=20201021_000005
 fpga_ver_win=20201022_000005
-ocloc_ver_win=27.20.100.8935
+ocloc_ver_win=27.20.100.9168
 
 [DRIVER VERSIONS]
 cpu_driver_lin=2020.11.11.0.04
 cpu_driver_win=2020.11.11.0.04
-gpu_driver_lin=21.03.18857
-gpu_driver_win=27.20.100.9030
+gpu_driver_lin=21.04.18912
+gpu_driver_win=27.20.100.9168
 fpga_driver_lin=2020.11.11.0.04
 fpga_driver_win=2020.11.11.0.04
 # NVidia CUDA driver

clang/include/clang/Basic/Attr.td

@@ -1272,11 +1272,6 @@ def SYCLIntelUseStallEnableClusters : InheritableAttr {
   let Spellings = [CXX11<"intel","use_stall_enable_clusters">];
   let LangOpts = [SYCLIsHost, SYCLIsDevice];
   let Subjects = SubjectList<[Function], ErrorDiag>;
-  let AdditionalMembers = [{
-    static const char *getName() {
-      return "stall_enable";
-    }
-  }];
   let Documentation = [SYCLIntelUseStallEnableClustersAttrDocs];
 }
 
@@ -1394,9 +1389,6 @@ def LoopUnrollHint : InheritableAttr {
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let HasCustomTypeTransform = 1;
   let AdditionalMembers = [{
-    static const char *getName() {
-      return "loop_unroll";
-    }
     std::string getDiagnosticName(const PrintingPolicy &Policy) const {
       std::string ValueName;
       llvm::raw_string_ostream OS(ValueName);
@@ -1820,9 +1812,6 @@ def SYCLIntelFPGAIVDep : Attr {
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let HasCustomTypeTransform = 1;
   let AdditionalMembers = [{
-    static const char *getName() {
-      return "ivdep";
-    }
     bool isDependent() const {
       return (getSafelenExpr() &&
               getSafelenExpr()->isInstantiationDependent()) ||
@@ -1863,11 +1852,6 @@ def SYCLIntelFPGAII : Attr {
   let Args = [ExprArgument<"IntervalExpr">];
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let HasCustomTypeTransform = 1;
-  let AdditionalMembers = [{
-    static const char *getName() {
-      return "ii";
-    }
-  }];
   let Documentation = [SYCLIntelFPGAIIAttrDocs];
 }
 
@@ -1877,11 +1861,6 @@ def SYCLIntelFPGAMaxConcurrency : Attr {
   let Args = [ExprArgument<"NThreadsExpr">];
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let HasCustomTypeTransform = 1;
-  let AdditionalMembers = [{
-    static const char *getName() {
-      return "max_concurrency";
-    }
-  }];
   let Documentation = [SYCLIntelFPGAMaxConcurrencyAttrDocs];
 }
 
@@ -1891,11 +1870,6 @@ def SYCLIntelFPGALoopCoalesce : Attr {
   let Args = [ExprArgument<"NExpr">];
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let HasCustomTypeTransform = 1;
-  let AdditionalMembers = [{
-    static const char *getName() {
-      return "loop_coalesce";
-    }
-  }];
   let Documentation = [SYCLIntelFPGALoopCoalesceAttrDocs];
 }
 
@@ -1904,11 +1878,6 @@ def SYCLIntelFPGADisableLoopPipelining : Attr {
                    CXX11<"intel","disable_loop_pipelining">];
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let HasCustomTypeTransform = 1;
-  let AdditionalMembers = [{
-    static const char *getName() {
-      return "disable_loop_pipelining";
-    }
-  }];
   let Documentation = [SYCLIntelFPGADisableLoopPipeliningAttrDocs];
 }
 
@@ -1918,11 +1887,6 @@ def SYCLIntelFPGAMaxInterleaving : Attr {
   let Args = [ExprArgument<"NExpr">];
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let HasCustomTypeTransform = 1;
-  let AdditionalMembers = [{
-    static const char *getName() {
-      return "max_interleaving";
-    }
-  }];
   let Documentation = [SYCLIntelFPGAMaxInterleavingAttrDocs];
 }
 
@@ -1932,23 +1896,13 @@ def SYCLIntelFPGASpeculatedIterations : Attr {
   let Args = [ExprArgument<"NExpr">];
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let HasCustomTypeTransform = 1;
-  let AdditionalMembers = [{
-    static const char *getName() {
-      return "speculated_iterations";
-    }
-  }];
   let Documentation = [SYCLIntelFPGASpeculatedIterationsAttrDocs];
 }
 
 def SYCLIntelFPGANofusion : Attr {
   let Spellings = [CXX11<"intel","nofusion">];
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let HasCustomTypeTransform = 1;
-  let AdditionalMembers = [{
-    static const char *getName() {
-      return "nofusion";
-    }
-  }];
   let Documentation = [SYCLIntelFPGANofusionAttrDocs];
 }