[ESIMD] Add driver option to control SYCL/ESIMD code splitting. (#6174)

This is needed to support invoke_simd processing in sycl-post-link.

Signed-off-by: Konstantin S Bobrovsky [email protected]

Author: kbobrovs

clang/include/clang/Driver/Options.td

@@ -2770,6 +2770,10 @@ def fsycl_device_code_split_EQ : Joined<["-"], "fsycl-device-code-split=">,
 def fsycl_device_code_split : Flag<["-"], "fsycl-device-code-split">, Alias<fsycl_device_code_split_EQ>,
   AliasArgs<["auto"]>, Flags<[CC1Option, CoreOption]>,
   HelpText<"Perform SYCL device code split in the 'auto' mode, i.e. use heuristic to distribute device code across modules">;
+def fsycl_device_code_split_esimd : Flag<["-"], "fsycl-device-code-split-esimd">,
+  Flags<[CoreOption]>, HelpText<"split ESIMD device code from SYCL into a separate device binary image (default). Has effect only for SPIR-based targets. (experimental)">;
+def fno_sycl_device_code_split_esimd : Flag<["-"], "fno-sycl-device-code-split-esimd">,
+  Flags<[CoreOption]>, HelpText<"do not split ESIMD and SYCL device code into separate device binary images. Has effect only for SPIR-based targets. (experimental)">;
 defm sycl_instrument_device_code
     : BoolFOption<"sycl-instrument-device-code",
           CodeGenOpts<"SPIRITTAnnotations">, DefaultFalse,

clang/lib/Driver/ToolChains/Clang.cpp

@@ -9382,11 +9382,16 @@ void SYCLPostLink::ConstructJob(Compilation &C, const JobAction &JA,
     addArgs(CmdArgs, TCArgs, {"-ir-output-only"});
   } else {
     assert(SYCLPostLink->getTrueType() == types::TY_Tempfiletable);
+    bool SplitEsimdByDefault = getToolChain().getTriple().isSPIR();
+    bool SplitEsimd = TCArgs.hasFlag(
+        options::OPT_fsycl_device_code_split_esimd,
+        options::OPT_fno_sycl_device_code_split_esimd, SplitEsimdByDefault);
     // Symbol file and specialization constant info generation is mandatory -
     // add options unconditionally
     addArgs(CmdArgs, TCArgs, {"-symbols"});
     addArgs(CmdArgs, TCArgs, {"-emit-exported-symbols"});
-    addArgs(CmdArgs, TCArgs, {"-split-esimd"});
+    if (SplitEsimd)
+      addArgs(CmdArgs, TCArgs, {"-split-esimd"});
     addArgs(CmdArgs, TCArgs, {"-lower-esimd"});
   }
   addArgs(CmdArgs, TCArgs,

clang/test/Driver/sycl-offload-with-split.c

@@ -338,3 +338,17 @@
 // RUN:   %clang    -### -fsycl -fsycl-targets=spir64_fpga-unknown-unknown %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER
 // RUN:   %clang_cl -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER
 // CHK-ESIMD-LOWER: sycl-post-link{{.*}} "-lower-esimd"
+
+// Check -f[no]sycl-device-code-split-esimd option's effect on sycl-post-link invocation
+// RUN:   %clang -### -fsycl -fsycl-device-code-split-esimd %s 2>&1 \
+// RUN:    | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT-ON
+// RUN:   %clang -### -fsycl -fno-sycl-device-code-split-esimd %s 2>&1 \
+// RUN:    | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT-OFF
+// RUN:   %clang -### -fsycl %s 2>&1 \
+// RUN:    | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT-DEFAULT
+// RUN:   %clang -### -fsycl -fsycl-targets=nvptx64-nvidia-cuda %s 2>&1 \
+// RUN:    | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT-NON-SPIRV
+// CHK-ESIMD-SPLIT-ON: sycl-post-link{{.*}} "-split-esimd"{{.*}} "-o"{{.*}}
+// CHK-ESIMD-SPLIT-OFF-NOT: sycl-post-link{{.*}} "-split-esimd"{{.*}}
+// CHK-ESIMD-SPLIT-DEFAULT: sycl-post-link{{.*}} "-split-esimd"{{.*}} "-o"{{.*}}
+// CHK-ESIMD-SPLIT-NON-SPIRV-NOT: sycl-post-link{{.*}} "-split-esimd"{{.*}}

sycl/doc/UsersManual.md

@@ -176,6 +176,16 @@ and not recommended to use in production environment.
     * auto - the compiler will use a heuristic to select the best way of
       splitting device code. This is default mode.
 
+**`-f[no-]sycl-device-code-split-esimd`** [EXPERIMENTAL]
+
+     Controls SYCL/ESIMD device code splitting. When enabled (this is the
+     default), SYCL and ESIMD entry points along with their call graphs are
+     put into separate device binary images. Otherwise, SYCL and ESIMD parts
+     of the device code are kept in the same device binary image and get
+     compiled by the Intel GPU compiler back end as a single module. This
+     option has effect only for SPIR-based targets and apps containing ESIMD
+     kernels.
+
 **`-fsycl-max-parallel-link-jobs=<N>`**
 
     Experimental feature. When specified, it informs the compiler