Update sycl test using new splat syntax

jsji · jsji · commit 6387a057a60f · 2024-11-22T17:22:54.000-08:00
After llvm/llvm-project@38fffa630ee8
diff --git a/llvm/test/SYCLLowerIR/ESIMD/lower_crash_zext.ll b/llvm/test/SYCLLowerIR/ESIMD/lower_crash_zext.ll
@@ -6,7 +6,7 @@
 
 define spir_func <32 x i16> @_Z3foov() {
 ; CHECK-LABEL: @_Z3foov(
-; CHECK-NEXT:    %call.i.i = zext <32 x i1> bitcast (<1 x i32> <i32 1717986918> to <32 x i1>) to <32 x i16>
+; CHECK-NEXT:    %call.i.i = zext <32 x i1> bitcast (<1 x i32> splat (i32 1717986918) to <32 x i1>) to <32 x i16>
 ; CHECK-NEXT:    ret <32 x i16> %call.i.i
 ;
   %call.i.i = call spir_func <32 x i16> @_Z19__esimd_unpack_maskILi32EEN2cl4sycl5INTEL3gpu11vector_typeItXT_EE4typeEj(i32 1717986918)
@@ -17,7 +17,7 @@ declare dso_local spir_func <32 x i16> @_Z19__esimd_unpack_maskILi32EEN2cl4sycl5
 
 define spir_func <16 x i16> @_Z3barv() {
 ; CHECK-LABEL: @_Z3barv(
-; CHECK:    %call.i.i = zext <16 x i1> bitcast (<1 x i16> <i16 15> to <16 x i1>) to <16 x i16>
+; CHECK:    %call.i.i = zext <16 x i1> bitcast (<1 x i16> splat (i16 15) to <16 x i1>) to <16 x i16>
 ;
   %call.i.i = call spir_func <16 x i16> @_Z19__esimd_unpack_maskILi16EEN2cl4sycl3ext5intel12experimental5esimd6detail11vector_typeItXT_EE4typeEj(i32 15)
   ret <16 x i16> %call.i.i
diff --git a/llvm/test/SYCLLowerIR/ESIMD/lower_intrins.ll b/llvm/test/SYCLLowerIR/ESIMD/lower_intrins.ll
@@ -48,7 +48,7 @@ define dso_local spir_func <16 x float>  @FUNC_11() {
   %a_2 = alloca  <8 x float>
   %2 = load  <8 x float>,  ptr %a_2
   %ret_val = call spir_func  <16 x float>  @_Z16__esimd_wrregionIfLi16ELi8ELi0ELi8ELi1ELi0EEN2cm3gen13__vector_typeIT_XT0_EE4typeES5_NS2_IS3_XT1_EE4typeEtNS2_ItXT1_EE4typeE(<16 x float> %1,  <8 x float> %2, i16 zeroext 0, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
-; CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x float> @llvm.genx.wrregionf.v16f32.v8f32.i16.v8i1(<16 x float> %{{[0-9a-zA-Z_.]+}}, <8 x float> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 8, i32 1, i16 0, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
+; CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x float> @llvm.genx.wrregionf.v16f32.v8f32.i16.v8i1(<16 x float> %{{[0-9a-zA-Z_.]+}}, <8 x float> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 8, i32 1, i16 0, i32 0, <8 x i1> splat (i1 true))
   ret <16 x float>  %ret_val
 }
 
@@ -209,7 +209,7 @@ define dso_local spir_func <16 x i32>  @FUNC_44() {
   %a_3 = alloca  <8 x i16>
   %3 = load  <8 x i16>,  ptr %a_3
   %ret_val = call spir_func <16 x i32> @_Z18__esimd_wrindirectIiLi16ELi8ELi0EEN2cl4sycl3ext5intel3gpu11vector_typeIT_XT0_EE4typeES7_NS4_IS5_XT1_EE4typeENS4_ItXT1_EE4typeESB_(<16 x i32> %1, <8 x i32> %2, <8 x i16> %3, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
-; CHECK: %{{[0-9a-zA-Z_.]+}} =  call <16 x i32> @llvm.genx.wrregioni.v16i32.v8i32.v8i16.v8i1(<16 x i32> %{{[0-9a-zA-Z_.]+}}, <8 x i32> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 1, i32 0, <8 x i16> %{{[0-9a-zA-Z_.]+}}, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
+; CHECK: %{{[0-9a-zA-Z_.]+}} =  call <16 x i32> @llvm.genx.wrregioni.v16i32.v8i32.v8i16.v8i1(<16 x i32> %{{[0-9a-zA-Z_.]+}}, <8 x i32> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 1, i32 0, <8 x i16> %{{[0-9a-zA-Z_.]+}}, i32 0, <8 x i1> splat (i1 true))
   ret <16 x i32>  %ret_val
 }
 
diff --git a/sycl-jit/test/kernel-fusion/check-remapping.ll b/sycl-jit/test/kernel-fusion/check-remapping.ll
@@ -385,7 +385,7 @@ declare !sycl.kernel.fused !31 !sycl.kernel.nd-ranges !25 !sycl.kernel.nd-range
 ; CHECK-LABEL: define internal spir_func i64 @__num_work_groups_remapper_1_10_1_1_10_1_1_3_48_1_1_2_1_1(
 ; CHECK-SAMEE:                                                                                          i32 %0) #[[ATTRS]] {
 ; CHECK-NEXT:   entry:
-; CHECK-NEXT:     %1 = extractelement <3 x i64> <i64 1, i64 1, i64 1>, i32 %0
+; CHECK-NEXT:     %1 = extractelement <3 x i64> splat (i64 1), i32 %0
 ; CHECK-NEXT:     ret i64 %1
 ; CHECK-NEXT:   }
 
diff --git a/sycl/test/check_device_code/esimd/intrins_trans.cpp b/sycl/test/check_device_code/esimd/intrins_trans.cpp
@@ -261,7 +261,7 @@ SYCL_ESIMD_FUNCTION SYCL_EXTERNAL simd<float, 16> foo() {
   auto d = __esimd_wrregion<float, 16 /*ret size*/, 8 /*write size*/,
                             0 /*vstride*/, 8 /*row width*/, 1 /*hstride*/>(
       c.data() /*dst*/, b.data() /*src*/, 0 /*offset*/);
-  // CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x float> @llvm.genx.wrregionf.v16f32.v8f32.i16.v8i1(<16 x float> %{{[0-9a-zA-Z_.]+}}, <8 x float> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 8, i32 1, i16 0, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
+  // CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x float> @llvm.genx.wrregionf.v16f32.v8f32.i16.v8i1(<16 x float> %{{[0-9a-zA-Z_.]+}}, <8 x float> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 8, i32 1, i16 0, i32 0, <8 x i1> splat (i1 true))
 
   simd<int, 32> va;
   va = media_block_load<int, 4, 8>(pA, x, y);
diff --git a/sycl/test/check_device_code/vector/vector_math_ops.cpp b/sycl/test/check_device_code/vector/vector_math_ops.cpp
@@ -269,7 +269,7 @@ SYCL_EXTERNAL auto TestMinus(vec<int, 4> a) { return -a; }
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    tail call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]])
 // CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr [[A]], align 16, !tbaa [[TBAA11]], !noalias [[META79]]
-// CHECK-NEXT:    [[NOT_I:%.*]] = xor <16 x i8> [[TMP0]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+// CHECK-NEXT:    [[NOT_I:%.*]] = xor <16 x i8> [[TMP0]], splat (i8 -1)
 // CHECK-NEXT:    store <16 x i8> [[NOT_I]], ptr addrspace(4) [[AGG_RESULT]], align 16, !tbaa [[TBAA11]], !alias.scope [[META79]]
 // CHECK-NEXT:    ret void
 //
diff --git a/sycl/test/esimd/ctor_codegen.cpp b/sycl/test/esimd/ctor_codegen.cpp
@@ -85,7 +85,7 @@ SYCL_EXTERNAL auto gee() SYCL_ESIMD_FUNCTION {
 // CHECK: define dso_local spir_func void @_Z3geev({{.*}} %[[RES:[a-zA-Z0-9_\.]+]]){{.*}} {
   simd<float, 2> val(-7);
   return val;
-// CHECK: store <2 x float> <float -7.000000e+00, float -7.000000e+00>, ptr addrspace(4) %[[RES]]
+// CHECK: store <2 x float> splat (float -7.000000e+00), ptr addrspace(4) %[[RES]]
 // CHECK-NEXT: ret void
 // CHECK-NEXT: }
 }
@@ -105,7 +105,7 @@ SYCL_EXTERNAL auto geemask() SYCL_ESIMD_FUNCTION {
 // CHECK: define dso_local spir_func void @_Z7geemaskv({{.*}} %[[RES:[a-zA-Z0-9_\.]+]]){{.*}} {
   simd_mask<2> val(1);
   return val;
-// CHECK: store <2 x i16> <i16 1, i16 1>, ptr addrspace(4) %[[RES]]
+// CHECK: store <2 x i16> splat (i16 1), ptr addrspace(4) %[[RES]]
 // CHECK-NEXT: ret void
 // CHECK-NEXT: }
 }
@@ -130,7 +130,7 @@ SYCL_EXTERNAL auto geehalf() SYCL_ESIMD_FUNCTION {
 // CHECK: define dso_local spir_func void @_Z7geehalfv({{.*}} %[[RES:[a-zA-Z0-9_\.]+]]){{.*}} {
   simd<half, 2> val(-7);
   return val;
-// CHECK: store <2 x half> <half 0xHC700, half 0xHC700>, ptr addrspace(4) %[[RES]]
+// CHECK: store <2 x half> splat (half 0xHC700), ptr addrspace(4) %[[RES]]
 // CHECK-NEXT: ret void
 // CHECK-NEXT: }
 }
