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vladimirlazvladimirlaz
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Merge remote-tracking branch 'intel_llvm/sycl' into backend_macro
2 parents ce06197 + 18f5643 commit 66662c6

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5,051 files changed

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‎.github/CODEOWNERS

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
* @bader
22

33
# Front-end compiler
4-
clang/ @premanandrao @elizabethandrews @AaronBallman
4+
clang/ @premanandrao @elizabethandrews @smanna12
55

66
# Driver
77
clang/**/Driver @mdtoguchi @AGindinson @hchilama
@@ -33,15 +33,15 @@ sycl/include/sycl/ext/intel/sub_group.hpp @Pennycook @AlexeySachkov
3333
sycl/include/sycl/ext/intel/sub_group_host.hpp @Pennycook @AlexeySachkov
3434

3535
# PI API
36-
sycl/include/CL/sycl/detail/pi.def @smaslov-intel
37-
sycl/include/CL/sycl/detail/pi.h @smaslov-intel
38-
sycl/include/CL/sycl/detail/pi.hpp @smaslov-intel
39-
sycl/include/CL/sycl/detail/pi* @smaslov-intel
40-
sycl/plugins/ @smaslov-intel
41-
sycl/source/detail/pi.cpp @smaslov-intel
42-
sycl/source/detail/plugin.hpp @smaslov-intel
43-
sycl/source/detail/posix_pi.cpp @smaslov-intel
44-
sycl/source/detail/windows_pi.cpp @smaslov-intel
36+
sycl/include/CL/sycl/detail/pi.def @smaslov-intel @againull
37+
sycl/include/CL/sycl/detail/pi.h @smaslov-intel @againull
38+
sycl/include/CL/sycl/detail/pi.hpp @smaslov-intel @againull
39+
sycl/include/CL/sycl/detail/pi* @smaslov-intel @againull
40+
sycl/plugins/ @smaslov-intel @againull
41+
sycl/source/detail/pi.cpp @smaslov-intel @againull
42+
sycl/source/detail/plugin.hpp @smaslov-intel @againull
43+
sycl/source/detail/posix_pi.cpp @smaslov-intel @againull
44+
sycl/source/detail/windows_pi.cpp @smaslov-intel @againull
4545

4646
# ESIMD CPU emulator plug-in
4747
sycl/plugins/esimd_cpu/ @kbobrovs @smaslov-intel
@@ -98,10 +98,10 @@ clang/tools/clang-offload-deps/ @sndmitriev @mlychkov @AlexeySachkov
9898
clang/tools/clang-offload-extract/ @sndmitriev @mlychkov @AlexeySachkov
9999

100100
# Explicit SIMD
101-
SYCLLowerIR/ @kbobrovs @DenisBakhvalov @kychendev
102-
esimd/ @kbobrovs @DenisBakhvalov @kychendev
103-
sycl/include/sycl/ext/intel/experimental/esimd.hpp @kbobrovs @DenisBakhvalov @kychendev
104-
sycl/doc/extensions/ExplicitSIMD/ @kbobrovs @DenisBakhvalov @kychendev
101+
SYCLLowerIR/ @kbobrovs @sndmitriev @kychendev @v-klochkov
102+
esimd/ @kbobrovs @v-klochkov @kychendev
103+
sycl/include/sycl/ext/intel/experimental/esimd.hpp @kbobrovs @v-klochkov @kychendev
104+
sycl/doc/extensions/ExplicitSIMD/ @kbobrovs @v-klochkov @kychendev
105105

106106
# ITT annotations
107107
llvm/lib/Transforms/Instrumentation/SPIRITTAnnotations.cpp @MrSidims @vzakhari

‎.github/workflows/linux_post_commit.yml

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,11 @@ jobs:
7878
run: |
7979
python3 $GITHUB_WORKSPACE/src/buildbot/check.py -w $GITHUB_WORKSPACE \
8080
-s $GITHUB_WORKSPACE/src -o $GITHUB_WORKSPACE/build -t check-llvm-spirv
81+
- name: check-xptifw
82+
if: always()
83+
run: |
84+
python3 $GITHUB_WORKSPACE/src/buildbot/check.py -w $GITHUB_WORKSPACE \
85+
-s $GITHUB_WORKSPACE/src -o $GITHUB_WORKSPACE/build -t check-xptifw
8186
- name: Pack
8287
run: tar -czvf llvm_sycl.tar.gz -C $GITHUB_WORKSPACE/build/install .
8388
- name: Upload artifacts

‎.mailmap

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@
2525
<[email protected]> <[email protected]>
2626
<[email protected]> <[email protected]>
2727
<[email protected]> <[email protected]>
28+
<[email protected]> <[email protected]>
2829
<[email protected]> <[email protected]>
2930
<[email protected]> <[email protected]>
3031
<[email protected]> <[email protected]>

‎buildbot/configure.py

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ def do_configure(args):
3232
sycl_build_pi_esimd_emulator = 'OFF'
3333
sycl_build_pi_hip = 'OFF'
3434
sycl_build_pi_hip_platform = 'AMD'
35+
sycl_clang_extra_flags = ''
3536
sycl_werror = 'ON'
3637
llvm_enable_assertions = 'ON'
3738
llvm_enable_doxygen = 'OFF'
@@ -40,6 +41,7 @@ def do_configure(args):
4041
llvm_enable_lld = 'OFF'
4142

4243
sycl_enable_xpti_tracing = 'ON'
44+
xpti_enable_werror = 'ON'
4345

4446
if args.ci_defaults:
4547
print("#############################################")
@@ -66,6 +68,8 @@ def do_configure(args):
6668
if args.hip_platform == 'AMD':
6769
llvm_targets_to_build += ';AMDGPU'
6870
libclc_targets_to_build += ';amdgcn--;amdgcn--amdhsa'
71+
if args.hip_amd_arch:
72+
sycl_clang_extra_flags += "-Xsycl-target-backend=amdgcn-amd-amdhsa --offload-arch="+args.hip_amd_arch
6973

7074
# The HIP plugin for AMD uses lld for linking
7175
llvm_enable_projects += ';lld'
@@ -79,6 +83,7 @@ def do_configure(args):
7983

8084
if args.no_werror:
8185
sycl_werror = 'OFF'
86+
xpti_enable_werror = 'OFF'
8287

8388
if args.no_assertions:
8489
llvm_enable_assertions = 'OFF'
@@ -123,7 +128,9 @@ def do_configure(args):
123128
"-DBUILD_SHARED_LIBS={}".format(llvm_build_shared_libs),
124129
"-DSYCL_ENABLE_XPTI_TRACING={}".format(sycl_enable_xpti_tracing),
125130
"-DLLVM_ENABLE_LLD={}".format(llvm_enable_lld),
126-
"-DSYCL_BUILD_PI_ESIMD_EMULATOR={}".format(sycl_build_pi_esimd_emulator)
131+
"-DSYCL_BUILD_PI_ESIMD_EMULATOR={}".format(sycl_build_pi_esimd_emulator),
132+
"-DXPTI_ENABLE_WERROR={}".format(xpti_enable_werror),
133+
"-DSYCL_CLANG_EXTRA_FLAGS={}".format(sycl_clang_extra_flags)
127134
]
128135

129136
if args.l0_headers and args.l0_loader:
@@ -185,6 +192,7 @@ def main():
185192
parser.add_argument("--cuda", action='store_true', help="switch from OpenCL to CUDA")
186193
parser.add_argument("--hip", action='store_true', help="switch from OpenCL to HIP")
187194
parser.add_argument("--hip-platform", type=str, choices=['AMD', 'NVIDIA'], default='AMD', help="choose hardware platform for HIP backend")
195+
parser.add_argument("--hip-amd-arch", type=str, help="Sets AMD gpu architecture for llvm lit tests, this is only needed for the HIP backend and AMD platform")
188196
parser.add_argument("--arm", action='store_true', help="build ARM support rather than x86")
189197
parser.add_argument("--enable-esimd-cpu-emulation", action='store_true', help="build with ESIMD_CPU emulation support")
190198
parser.add_argument("--no-assertions", action='store_true', help="build without assertions")

‎buildbot/dependency.conf

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
[VERSIONS]
2-
# https://github.com/intel/llvm/releases/download/2021-WW26/oclcpuexp-2021.12.6.0.19_rel.tar.gz
3-
ocl_cpu_rt_ver=2021.12.6.0.19
4-
# https://github.com/intel/llvm/releases/download/2021-WW26/win-oclcpuexp-2021.12.6.0.19_rel.zip
5-
ocl_cpu_rt_ver_win=2021.12.6.0.19
2+
# https://github.com/intel/llvm/releases/download/2021-WW40/oclcpuexp-2021.12.9.0.24_rel.tar.gz
3+
ocl_cpu_rt_ver=2021.12.9.0.24
4+
# https://github.com/intel/llvm/releases/download/2021-WW40/win-oclcpuexp-2021.12.9.0.24_rel.zip
5+
ocl_cpu_rt_ver_win=2021.12.9.0.24
66
# Same GPU driver supports Level Zero and OpenCL
77
# https://github.com/intel/compute-runtime/releases/tag/21.37.20939
88
ocl_gpu_rt_ver=21.37.20939
@@ -14,26 +14,26 @@ intel_sycl_ver=build
1414
# TBB binaries can be built from sources following instructions under
1515
# https://github.com/oneapi-src/oneTBB/blob/master/cmake/README.md
1616
# or downloaded using links below:
17-
# https://github.com/oneapi-src/oneTBB/releases/download/v2021.2.0/oneapi-tbb-2021.2.0-lin.tgz
18-
tbb_ver=2021.3.0.418
19-
# https://github.com/oneapi-src/oneTBB/releases/download/v2021.2.0/oneapi-tbb-2021.2.0-win.zip
20-
tbb_ver_win=2021.3.0.418
17+
# https://github.com/oneapi-src/oneTBB/releases/download/v2021.3.0/oneapi-tbb-2021.3.0-lin.tgz
18+
tbb_ver=2021.4.0.569
19+
# https://github.com/oneapi-src/oneTBB/releases/download/v2021.3.0/oneapi-tbb-2021.3.0-win.zip
20+
tbb_ver_win=2021.4.0.561
2121

22-
# https://github.com/intel/llvm/releases/download/2021-WW26/fpgaemu-2021.12.6.0.19_rel.tar.gz
23-
ocl_fpga_emu_ver=2021.12.6.0.19
24-
# https://github.com/intel/llvm/releases/download/2021-WW26/win-fpgaemu-2021.12.6.0.19_rel.zip
25-
ocl_fpga_emu_ver_win=2021.12.6.0.19
26-
fpga_ver=20210519_000004
27-
fpga_ver_win=20210509_000006
22+
# https://github.com/intel/llvm/releases/download/2021-WW40/fpgaemu-2021.12.9.0.24_rel.tar.gz
23+
ocl_fpga_emu_ver=2021.12.9.0.24
24+
# https://github.com/intel/llvm/releases/download/2021-WW40/win-fpgaemu-2021.12.9.0.24_rel.zip
25+
ocl_fpga_emu_ver_win=2021.12.9.0.24
26+
fpga_ver=20210805_000004
27+
fpga_ver_win=20210805_000004
2828
ocloc_ver_win=27.20.100.9168
2929

3030
[DRIVER VERSIONS]
31-
cpu_driver_lin=2021.12.6.0.19
32-
cpu_driver_win=2021.12.6.0.19
31+
cpu_driver_lin=2021.12.9.0.24
32+
cpu_driver_win=2021.12.9.0.24
3333
gpu_driver_lin=21.37.20939
3434
gpu_driver_win=30.0.100.9864
35-
fpga_driver_lin=2021.12.6.0.19
36-
fpga_driver_win=2021.12.6.0.19
35+
fpga_driver_lin=2021.12.9.0.24
36+
fpga_driver_win=2021.12.9.0.24
3737
# NVidia CUDA driver
3838
# TODO provide URL for CUDA driver
3939
nvidia_gpu_driver_lin=435.21

‎clang-tools-extra/clang-doc/BitcodeReader.cpp

Lines changed: 27 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -17,13 +17,14 @@ namespace doc {
1717

1818
using Record = llvm::SmallVector<uint64_t, 1024>;
1919

20-
llvm::Error decodeRecord(Record R, llvm::SmallVectorImpl<char> &Field,
20+
llvm::Error decodeRecord(const Record &R, llvm::SmallVectorImpl<char> &Field,
2121
llvm::StringRef Blob) {
2222
Field.assign(Blob.begin(), Blob.end());
2323
return llvm::Error::success();
2424
}
2525

26-
llvm::Error decodeRecord(Record R, SymbolID &Field, llvm::StringRef Blob) {
26+
llvm::Error decodeRecord(const Record &R, SymbolID &Field,
27+
llvm::StringRef Blob) {
2728
if (R[0] != BitCodeConstants::USRHashSize)
2829
return llvm::createStringError(llvm::inconvertibleErrorCode(),
2930
"incorrect USR size");
@@ -35,20 +36,20 @@ llvm::Error decodeRecord(Record R, SymbolID &Field, llvm::StringRef Blob) {
3536
return llvm::Error::success();
3637
}
3738

38-
llvm::Error decodeRecord(Record R, bool &Field, llvm::StringRef Blob) {
39+
llvm::Error decodeRecord(const Record &R, bool &Field, llvm::StringRef Blob) {
3940
Field = R[0] != 0;
4041
return llvm::Error::success();
4142
}
4243

43-
llvm::Error decodeRecord(Record R, int &Field, llvm::StringRef Blob) {
44+
llvm::Error decodeRecord(const Record &R, int &Field, llvm::StringRef Blob) {
4445
if (R[0] > INT_MAX)
4546
return llvm::createStringError(llvm::inconvertibleErrorCode(),
4647
"integer too large to parse");
4748
Field = (int)R[0];
4849
return llvm::Error::success();
4950
}
5051

51-
llvm::Error decodeRecord(Record R, AccessSpecifier &Field,
52+
llvm::Error decodeRecord(const Record &R, AccessSpecifier &Field,
5253
llvm::StringRef Blob) {
5354
switch (R[0]) {
5455
case AS_public:
@@ -63,7 +64,8 @@ llvm::Error decodeRecord(Record R, AccessSpecifier &Field,
6364
}
6465
}
6566

66-
llvm::Error decodeRecord(Record R, TagTypeKind &Field, llvm::StringRef Blob) {
67+
llvm::Error decodeRecord(const Record &R, TagTypeKind &Field,
68+
llvm::StringRef Blob) {
6769
switch (R[0]) {
6870
case TTK_Struct:
6971
case TTK_Interface:
@@ -78,7 +80,7 @@ llvm::Error decodeRecord(Record R, TagTypeKind &Field, llvm::StringRef Blob) {
7880
}
7981
}
8082

81-
llvm::Error decodeRecord(Record R, llvm::Optional<Location> &Field,
83+
llvm::Error decodeRecord(const Record &R, llvm::Optional<Location> &Field,
8284
llvm::StringRef Blob) {
8385
if (R[0] > INT_MAX)
8486
return llvm::createStringError(llvm::inconvertibleErrorCode(),
@@ -87,7 +89,8 @@ llvm::Error decodeRecord(Record R, llvm::Optional<Location> &Field,
8789
return llvm::Error::success();
8890
}
8991

90-
llvm::Error decodeRecord(Record R, InfoType &Field, llvm::StringRef Blob) {
92+
llvm::Error decodeRecord(const Record &R, InfoType &Field,
93+
llvm::StringRef Blob) {
9194
switch (auto IT = static_cast<InfoType>(R[0])) {
9295
case InfoType::IT_namespace:
9396
case InfoType::IT_record:
@@ -101,7 +104,8 @@ llvm::Error decodeRecord(Record R, InfoType &Field, llvm::StringRef Blob) {
101104
"invalid value for InfoType");
102105
}
103106

104-
llvm::Error decodeRecord(Record R, FieldId &Field, llvm::StringRef Blob) {
107+
llvm::Error decodeRecord(const Record &R, FieldId &Field,
108+
llvm::StringRef Blob) {
105109
switch (auto F = static_cast<FieldId>(R[0])) {
106110
case FieldId::F_namespace:
107111
case FieldId::F_parent:
@@ -117,14 +121,15 @@ llvm::Error decodeRecord(Record R, FieldId &Field, llvm::StringRef Blob) {
117121
"invalid value for FieldId");
118122
}
119123

120-
llvm::Error decodeRecord(Record R,
124+
llvm::Error decodeRecord(const Record &R,
121125
llvm::SmallVectorImpl<llvm::SmallString<16>> &Field,
122126
llvm::StringRef Blob) {
123127
Field.push_back(Blob);
124128
return llvm::Error::success();
125129
}
126130

127-
llvm::Error decodeRecord(Record R, llvm::SmallVectorImpl<Location> &Field,
131+
llvm::Error decodeRecord(const Record &R,
132+
llvm::SmallVectorImpl<Location> &Field,
128133
llvm::StringRef Blob) {
129134
if (R[0] > INT_MAX)
130135
return llvm::createStringError(llvm::inconvertibleErrorCode(),
@@ -133,15 +138,15 @@ llvm::Error decodeRecord(Record R, llvm::SmallVectorImpl<Location> &Field,
133138
return llvm::Error::success();
134139
}
135140

136-
llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
141+
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
137142
const unsigned VersionNo) {
138143
if (ID == VERSION && R[0] == VersionNo)
139144
return llvm::Error::success();
140145
return llvm::createStringError(llvm::inconvertibleErrorCode(),
141146
"mismatched bitcode version number");
142147
}
143148

144-
llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
149+
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
145150
NamespaceInfo *I) {
146151
switch (ID) {
147152
case NAMESPACE_USR:
@@ -156,7 +161,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
156161
}
157162
}
158163

159-
llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
164+
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
160165
RecordInfo *I) {
161166
switch (ID) {
162167
case RECORD_USR:
@@ -179,7 +184,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
179184
}
180185
}
181186

182-
llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
187+
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
183188
BaseRecordInfo *I) {
184189
switch (ID) {
185190
case BASE_RECORD_USR:
@@ -202,7 +207,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
202207
}
203208
}
204209

205-
llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
210+
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
206211
EnumInfo *I) {
207212
switch (ID) {
208213
case ENUM_USR:
@@ -223,7 +228,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
223228
}
224229
}
225230

226-
llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
231+
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
227232
FunctionInfo *I) {
228233
switch (ID) {
229234
case FUNCTION_USR:
@@ -244,12 +249,12 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
244249
}
245250
}
246251

247-
llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
252+
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
248253
TypeInfo *I) {
249254
return llvm::Error::success();
250255
}
251256

252-
llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
257+
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
253258
FieldTypeInfo *I) {
254259
switch (ID) {
255260
case FIELD_TYPE_NAME:
@@ -260,7 +265,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
260265
}
261266
}
262267

263-
llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
268+
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
264269
MemberTypeInfo *I) {
265270
switch (ID) {
266271
case MEMBER_TYPE_NAME:
@@ -273,7 +278,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
273278
}
274279
}
275280

276-
llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
281+
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
277282
CommentInfo *I) {
278283
switch (ID) {
279284
case COMMENT_KIND:
@@ -304,7 +309,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
304309
}
305310
}
306311

307-
llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
312+
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
308313
Reference *I, FieldId &F) {
309314
switch (ID) {
310315
case REFERENCE_USR:

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