@@ -552,11 +552,11 @@ MDNode *LoopInfo::createMetadata(
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}
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// Setting max_concurrency attribute with number of threads
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- if (Attrs.SYCLMaxConcurrencyEnable ) {
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- Metadata *Vals[] = {MDString::get (Ctx, " llvm.loop.max_concurrency.count " ),
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- ConstantAsMetadata ::get (ConstantInt::get (
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- llvm::Type::getInt32Ty (Ctx),
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- Attrs.SYCLMaxConcurrencyNThreads ))};
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+ if (Attrs.SYCLMaxConcurrencyNThreads ) {
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+ Metadata *Vals[] = {
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+ MDString ::get (Ctx, " llvm.loop.max_concurrency.count " ),
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+ ConstantAsMetadata::get ( ConstantInt::get (
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+ llvm::Type::getInt32Ty (Ctx), * Attrs.SYCLMaxConcurrencyNThreads ))};
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LoopProperties.push_back (MDNode::get (Ctx, Vals));
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}
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@@ -582,11 +582,11 @@ MDNode *LoopInfo::createMetadata(
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LoopProperties.push_back (MDNode::get (Ctx, Vals));
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}
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- if (Attrs.SYCLMaxInterleavingEnable ) {
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+ if (Attrs.SYCLMaxInterleavingNInvocations ) {
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Metadata *Vals[] = {MDString::get (Ctx, " llvm.loop.max_interleaving.count" ),
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ConstantAsMetadata::get (ConstantInt::get (
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llvm::Type::getInt32Ty (Ctx),
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- Attrs.SYCLMaxInterleavingNInvocations ))};
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+ * Attrs.SYCLMaxInterleavingNInvocations ))};
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LoopProperties.push_back (MDNode::get (Ctx, Vals));
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}
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@@ -596,16 +596,16 @@ MDNode *LoopInfo::createMetadata(
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LoopProperties.push_back (MDNode::get (Ctx, Vals));
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}
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- if (Attrs.SYCLSpeculatedIterationsEnable ) {
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+ if (Attrs.SYCLSpeculatedIterationsNIterations ) {
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Metadata *Vals[] = {
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MDString::get (Ctx, " llvm.loop.intel.speculated.iterations.count" ),
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ConstantAsMetadata::get (
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ConstantInt::get (llvm::Type::getInt32Ty (Ctx),
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- Attrs.SYCLSpeculatedIterationsNIterations ))};
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+ * Attrs.SYCLSpeculatedIterationsNIterations ))};
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LoopProperties.push_back (MDNode::get (Ctx, Vals));
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}
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- for (auto &VC : Attrs.SYCLIntelFPGAVariantCount ) {
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+ for (const auto &VC : Attrs.SYCLIntelFPGAVariantCount ) {
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Metadata *Vals[] = {MDString::get (Ctx, VC.first ),
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ConstantAsMetadata::get (ConstantInt::get (
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llvm::Type::getInt32Ty (Ctx), VC.second ))};
@@ -622,15 +622,12 @@ LoopAttributes::LoopAttributes(bool IsParallel)
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UnrollAndJamEnable(LoopAttributes::Unspecified),
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VectorizePredicateEnable(LoopAttributes::Unspecified), VectorizeWidth(0 ),
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VectorizeScalable(LoopAttributes::Unspecified), InterleaveCount(0 ),
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- SYCLIInterval(0 ), SYCLMaxConcurrencyEnable(false ),
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- SYCLMaxConcurrencyNThreads(0 ), SYCLLoopCoalesceEnable(false ),
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+ SYCLIInterval(0 ), SYCLLoopCoalesceEnable(false ),
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SYCLLoopCoalesceNLevels(0 ), SYCLLoopPipeliningDisable(false ),
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- SYCLMaxInterleavingEnable(false ), SYCLMaxInterleavingNInvocations(0 ),
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- SYCLSpeculatedIterationsEnable(false ),
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- SYCLSpeculatedIterationsNIterations(0 ), UnrollCount(0 ),
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- UnrollAndJamCount(0 ), DistributeEnable(LoopAttributes::Unspecified),
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- PipelineDisabled(false ), PipelineInitiationInterval(0 ),
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- SYCLNofusionEnable(false ), MustProgress(false ) {}
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+ UnrollCount(0 ), UnrollAndJamCount(0 ),
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+ DistributeEnable(LoopAttributes::Unspecified), PipelineDisabled(false ),
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+ PipelineInitiationInterval(0 ), SYCLNofusionEnable(false ),
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+ MustProgress(false ) {}
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void LoopAttributes::clear () {
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IsParallel = false ;
@@ -640,15 +637,12 @@ void LoopAttributes::clear() {
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GlobalSYCLIVDepInfo.reset ();
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ArraySYCLIVDepInfo.clear ();
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SYCLIInterval = 0 ;
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- SYCLMaxConcurrencyEnable = false ;
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- SYCLMaxConcurrencyNThreads = 0 ;
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+ SYCLMaxConcurrencyNThreads.reset ();
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SYCLLoopCoalesceEnable = false ;
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SYCLLoopCoalesceNLevels = 0 ;
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SYCLLoopPipeliningDisable = false ;
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- SYCLMaxInterleavingEnable = false ;
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- SYCLMaxInterleavingNInvocations = 0 ;
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- SYCLSpeculatedIterationsEnable = false ;
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- SYCLSpeculatedIterationsNIterations = 0 ;
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+ SYCLMaxInterleavingNInvocations.reset ();
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+ SYCLSpeculatedIterationsNIterations.reset ();
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SYCLIntelFPGAVariantCount.clear ();
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UnrollCount = 0 ;
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UnrollAndJamCount = 0 ;
@@ -679,14 +673,12 @@ LoopInfo::LoopInfo(BasicBlock *Header, const LoopAttributes &Attrs,
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Attrs.VectorizeScalable == LoopAttributes::Unspecified &&
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Attrs.InterleaveCount == 0 && !Attrs.GlobalSYCLIVDepInfo .hasValue () &&
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Attrs.ArraySYCLIVDepInfo .empty () && Attrs.SYCLIInterval == 0 &&
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- Attrs.SYCLMaxConcurrencyEnable == false &&
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+ ! Attrs.SYCLMaxConcurrencyNThreads &&
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Attrs.SYCLLoopCoalesceEnable == false &&
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Attrs.SYCLLoopCoalesceNLevels == 0 &&
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Attrs.SYCLLoopPipeliningDisable == false &&
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- Attrs.SYCLMaxInterleavingEnable == false &&
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- Attrs.SYCLMaxInterleavingNInvocations == 0 &&
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- Attrs.SYCLSpeculatedIterationsEnable == false &&
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- Attrs.SYCLSpeculatedIterationsNIterations == 0 &&
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+ !Attrs.SYCLMaxInterleavingNInvocations &&
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+ !Attrs.SYCLSpeculatedIterationsNIterations &&
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Attrs.SYCLIntelFPGAVariantCount .empty () && Attrs.UnrollCount == 0 &&
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Attrs.UnrollAndJamCount == 0 && !Attrs.PipelineDisabled &&
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Attrs.PipelineInitiationInterval == 0 &&
@@ -1025,59 +1017,60 @@ void LoopInfoStack::push(BasicBlock *Header, clang::ASTContext &Ctx,
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IntelFPGAIVDep->getArrayDecl ());
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if (const auto *IntelFPGAII =
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- dyn_cast<SYCLIntelFPGAInitiationIntervalAttr>(A))
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- setSYCLIInterval (IntelFPGAII->getIntervalExpr ()
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- ->getIntegerConstantExpr (Ctx)
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- ->getSExtValue ());
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+ dyn_cast<SYCLIntelFPGAInitiationIntervalAttr>(A)) {
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+ const auto *CE = cast<ConstantExpr>(IntelFPGAII->getIntervalExpr ());
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+ llvm::APSInt ArgVal = CE->getResultAsAPSInt ();
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+ setSYCLIInterval (ArgVal.getSExtValue ());
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+ }
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if (const auto *IntelFPGAMaxConcurrency =
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dyn_cast<SYCLIntelFPGAMaxConcurrencyAttr>(A)) {
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- setSYCLMaxConcurrencyEnable ();
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- setSYCLMaxConcurrencyNThreads (IntelFPGAMaxConcurrency->getNThreadsExpr ()
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- -> getIntegerConstantExpr (Ctx)
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- -> getSExtValue ());
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+ const auto *CE =
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+ cast<ConstantExpr> (IntelFPGAMaxConcurrency->getNThreadsExpr ());
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+ llvm::APSInt ArgVal = CE-> getResultAsAPSInt ();
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+ setSYCLMaxConcurrencyNThreads (ArgVal. getSExtValue ());
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}
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if (const auto *IntelFPGALoopCountAvg =
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dyn_cast<SYCLIntelFPGALoopCountAttr>(A)) {
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- unsigned int Count = IntelFPGALoopCountAvg-> getNTripCount ()
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- -> getIntegerConstantExpr (Ctx)
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- -> getSExtValue ();
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+ const auto *CE =
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+ cast<ConstantExpr>(IntelFPGALoopCountAvg-> getNTripCount ());
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+ llvm::APSInt ArgVal = CE-> getResultAsAPSInt ();
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const char *Var = IntelFPGALoopCountAvg->isMax ()
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? " llvm.loop.intel.loopcount_max"
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: IntelFPGALoopCountAvg->isMin ()
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? " llvm.loop.intel.loopcount_min"
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: " llvm.loop.intel.loopcount_avg" ;
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- setSYCLIntelFPGAVariantCount (Var, Count );
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+ setSYCLIntelFPGAVariantCount (Var, ArgVal. getSExtValue () );
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}
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if (const auto *IntelFPGALoopCoalesce =
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dyn_cast<SYCLIntelFPGALoopCoalesceAttr>(A)) {
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- if (auto *LCE = IntelFPGALoopCoalesce->getNExpr ())
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- setSYCLLoopCoalesceNLevels (
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- LCE->getIntegerConstantExpr (Ctx)->getSExtValue ());
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- else
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+ if (const auto *LCE = IntelFPGALoopCoalesce->getNExpr ()) {
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+ const auto *CE = cast<ConstantExpr>(LCE);
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+ llvm::APSInt ArgVal = CE->getResultAsAPSInt ();
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+ setSYCLLoopCoalesceNLevels (ArgVal.getSExtValue ());
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+ } else {
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setSYCLLoopCoalesceEnable ();
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+ }
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}
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if (isa<SYCLIntelFPGADisableLoopPipeliningAttr>(A))
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setSYCLLoopPipeliningDisable ();
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if (const auto *IntelFPGAMaxInterleaving =
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dyn_cast<SYCLIntelFPGAMaxInterleavingAttr>(A)) {
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- setSYCLMaxInterleavingEnable ();
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- setSYCLMaxInterleavingNInvocations (IntelFPGAMaxInterleaving->getNExpr ()
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- ->getIntegerConstantExpr (Ctx)
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- ->getSExtValue ());
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+ const auto *CE = cast<ConstantExpr>(IntelFPGAMaxInterleaving->getNExpr ());
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+ llvm::APSInt ArgVal = CE->getResultAsAPSInt ();
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+ setSYCLMaxInterleavingNInvocations (ArgVal.getSExtValue ());
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}
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if (const auto *IntelFPGASpeculatedIterations =
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dyn_cast<SYCLIntelFPGASpeculatedIterationsAttr>(A)) {
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- setSYCLSpeculatedIterationsEnable ();
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- setSYCLSpeculatedIterationsNIterations (
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- IntelFPGASpeculatedIterations->getNExpr ()
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- ->getIntegerConstantExpr (Ctx)
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- ->getSExtValue ());
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+ const auto *CE =
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+ cast<ConstantExpr>(IntelFPGASpeculatedIterations->getNExpr ());
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+ llvm::APSInt ArgVal = CE->getResultAsAPSInt ();
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+ setSYCLSpeculatedIterationsNIterations (ArgVal.getSExtValue ());
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}
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if (isa<SYCLIntelFPGANofusionAttr>(A))
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