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Merge commit '7a8090c037255b54895d61df2eb141fee48d6d83' into llvmspirv_pulldown
2 parents 071edb1 + 7a8090c commit 6ebc051

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13 files changed

+126
-138
lines changed

13 files changed

+126
-138
lines changed

‎flang/lib/Semantics/check-omp-structure.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2575,8 +2575,8 @@ void OmpStructureChecker::CheckCancellationNest(
25752575
}
25762576
break;
25772577
default:
2578-
// This should have been diagnosed by this point.
2579-
llvm_unreachable("Unexpected directive");
2578+
// This is diagnosed later.
2579+
return;
25802580
}
25812581
if (!eligibleCancellation) {
25822582
context_.Say(source,
@@ -2614,8 +2614,8 @@ void OmpStructureChecker::CheckCancellationNest(
26142614
parser::ToUpperCaseLetters(typeName.str()));
26152615
break;
26162616
default:
2617-
// This should have been diagnosed by this point.
2618-
llvm_unreachable("Unexpected directive");
2617+
// This is diagnosed later.
2618+
return;
26192619
}
26202620
}
26212621
}

‎flang/test/Semantics/OpenMP/cancel-bad-cancel-type.f90

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
!RUN: %python %S/../test_errors.py %s %flang_fc1 %openmp_flags
2+
3+
program test
4+
!ERROR: PARALLEL DO is not a cancellable construct
5+
!$omp cancel parallel do
6+
end

‎libclc/opencl/include/clc/opencl/math/frexp.h

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,5 +6,8 @@
66
//
77
//===----------------------------------------------------------------------===//
88

9-
#define __CLC_BODY <clc/opencl/math/frexp.inc>
9+
#define __CLC_FUNCTION frexp
10+
#define __CLC_BODY <clc/math/unary_decl_with_int_ptr.inc>
1011
#include <clc/math/gentype.inc>
12+
13+
#undef __CLC_FUNCTION

‎libclc/opencl/include/clc/opencl/math/frexp.inc

Lines changed: 0 additions & 14 deletions
This file was deleted.

‎llvm/docs/AArch64SME.rst

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -213,12 +213,14 @@ Instruction Selection Nodes
213213

214214
.. code-block:: none
215215
216-
AArch64ISD::SMSTART Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
217-
AArch64ISD::SMSTOP Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
218-
219-
The ``SMSTART/SMSTOP`` nodes take ``CurrentState`` and ``ExpectedState`` operand for
220-
the case of a conditional SMSTART/SMSTOP. The instruction will only be executed
221-
if CurrentState != ExpectedState.
216+
AArch64ISD::SMSTART Chain, [SM|ZA|Both][, RegMask]
217+
AArch64ISD::SMSTOP Chain, [SM|ZA|Both][, RegMask]
218+
AArch64ISD::COND_SMSTART Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
219+
AArch64ISD::COND_SMSTOP Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
220+
221+
The ``COND_SMSTART/COND_SMSTOP`` nodes additionally take ``CurrentState`` and
222+
``ExpectedState``, in this case the instruction will only be executed if
223+
``CurrentState != ExpectedState``.
222224

223225
When ``CurrentState`` and ``ExpectedState`` can be evaluated at compile-time
224226
(i.e. they are both constants) then an unconditional ``smstart/smstop``

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 0 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -7216,57 +7216,6 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
72167216
}
72177217
break;
72187218
}
7219-
case AArch64ISD::SVE_LD2_MERGE_ZERO: {
7220-
if (VT == MVT::nxv16i8) {
7221-
SelectPredicatedLoad(Node, 2, 0, AArch64::LD2B_IMM, AArch64::LD2B);
7222-
return;
7223-
} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
7224-
VT == MVT::nxv8bf16) {
7225-
SelectPredicatedLoad(Node, 2, 1, AArch64::LD2H_IMM, AArch64::LD2H);
7226-
return;
7227-
} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
7228-
SelectPredicatedLoad(Node, 2, 2, AArch64::LD2W_IMM, AArch64::LD2W);
7229-
return;
7230-
} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
7231-
SelectPredicatedLoad(Node, 2, 3, AArch64::LD2D_IMM, AArch64::LD2D);
7232-
return;
7233-
}
7234-
break;
7235-
}
7236-
case AArch64ISD::SVE_LD3_MERGE_ZERO: {
7237-
if (VT == MVT::nxv16i8) {
7238-
SelectPredicatedLoad(Node, 3, 0, AArch64::LD3B_IMM, AArch64::LD3B);
7239-
return;
7240-
} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
7241-
VT == MVT::nxv8bf16) {
7242-
SelectPredicatedLoad(Node, 3, 1, AArch64::LD3H_IMM, AArch64::LD3H);
7243-
return;
7244-
} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
7245-
SelectPredicatedLoad(Node, 3, 2, AArch64::LD3W_IMM, AArch64::LD3W);
7246-
return;
7247-
} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
7248-
SelectPredicatedLoad(Node, 3, 3, AArch64::LD3D_IMM, AArch64::LD3D);
7249-
return;
7250-
}
7251-
break;
7252-
}
7253-
case AArch64ISD::SVE_LD4_MERGE_ZERO: {
7254-
if (VT == MVT::nxv16i8) {
7255-
SelectPredicatedLoad(Node, 4, 0, AArch64::LD4B_IMM, AArch64::LD4B);
7256-
return;
7257-
} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
7258-
VT == MVT::nxv8bf16) {
7259-
SelectPredicatedLoad(Node, 4, 1, AArch64::LD4H_IMM, AArch64::LD4H);
7260-
return;
7261-
} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
7262-
SelectPredicatedLoad(Node, 4, 2, AArch64::LD4W_IMM, AArch64::LD4W);
7263-
return;
7264-
} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
7265-
SelectPredicatedLoad(Node, 4, 3, AArch64::LD4D_IMM, AArch64::LD4D);
7266-
return;
7267-
}
7268-
break;
7269-
}
72707219
}
72717220

72727221
// Select the default instruction
@@ -7340,15 +7289,6 @@ static EVT getMemVTFromNode(LLVMContext &Ctx, SDNode *Root) {
73407289
return cast<VTSDNode>(Root->getOperand(3))->getVT();
73417290
case AArch64ISD::ST1_PRED:
73427291
return cast<VTSDNode>(Root->getOperand(4))->getVT();
7343-
case AArch64ISD::SVE_LD2_MERGE_ZERO:
7344-
return getPackedVectorTypeFromPredicateType(
7345-
Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/2);
7346-
case AArch64ISD::SVE_LD3_MERGE_ZERO:
7347-
return getPackedVectorTypeFromPredicateType(
7348-
Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/3);
7349-
case AArch64ISD::SVE_LD4_MERGE_ZERO:
7350-
return getPackedVectorTypeFromPredicateType(
7351-
Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/4);
73527292
default:
73537293
break;
73547294
}

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -2726,6 +2726,8 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
27262726
MAKE_CASE(AArch64ISD::VG_RESTORE)
27272727
MAKE_CASE(AArch64ISD::SMSTART)
27282728
MAKE_CASE(AArch64ISD::SMSTOP)
2729+
MAKE_CASE(AArch64ISD::COND_SMSTART)
2730+
MAKE_CASE(AArch64ISD::COND_SMSTOP)
27292731
MAKE_CASE(AArch64ISD::RESTORE_ZA)
27302732
MAKE_CASE(AArch64ISD::RESTORE_ZT)
27312733
MAKE_CASE(AArch64ISD::SAVE_ZT)
@@ -2955,9 +2957,6 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
29552957
MAKE_CASE(AArch64ISD::LDFF1S_MERGE_ZERO)
29562958
MAKE_CASE(AArch64ISD::LD1RQ_MERGE_ZERO)
29572959
MAKE_CASE(AArch64ISD::LD1RO_MERGE_ZERO)
2958-
MAKE_CASE(AArch64ISD::SVE_LD2_MERGE_ZERO)
2959-
MAKE_CASE(AArch64ISD::SVE_LD3_MERGE_ZERO)
2960-
MAKE_CASE(AArch64ISD::SVE_LD4_MERGE_ZERO)
29612960
MAKE_CASE(AArch64ISD::GLD1_MERGE_ZERO)
29622961
MAKE_CASE(AArch64ISD::GLD1_SCALED_MERGE_ZERO)
29632962
MAKE_CASE(AArch64ISD::GLD1_SXTW_MERGE_ZERO)
@@ -3017,7 +3016,6 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
30173016
MAKE_CASE(AArch64ISD::CTLZ_MERGE_PASSTHRU)
30183017
MAKE_CASE(AArch64ISD::CTPOP_MERGE_PASSTHRU)
30193018
MAKE_CASE(AArch64ISD::DUP_MERGE_PASSTHRU)
3020-
MAKE_CASE(AArch64ISD::INDEX_VECTOR)
30213019
MAKE_CASE(AArch64ISD::ADDP)
30223020
MAKE_CASE(AArch64ISD::SADDLP)
30233021
MAKE_CASE(AArch64ISD::UADDLP)
@@ -6033,14 +6031,12 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_VOID(SDValue Op,
60336031
return DAG.getNode(
60346032
AArch64ISD::SMSTART, DL, MVT::Other,
60356033
Op->getOperand(0), // Chain
6036-
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
6037-
DAG.getConstant(AArch64SME::Always, DL, MVT::i64));
6034+
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
60386035
case Intrinsic::aarch64_sme_za_disable:
60396036
return DAG.getNode(
60406037
AArch64ISD::SMSTOP, DL, MVT::Other,
60416038
Op->getOperand(0), // Chain
6042-
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
6043-
DAG.getConstant(AArch64SME::Always, DL, MVT::i64));
6039+
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
60446040
}
60456041
}
60466042

@@ -8927,18 +8923,22 @@ SDValue AArch64TargetLowering::changeStreamingMode(SelectionDAG &DAG, SDLoc DL,
89278923
SDValue RegMask = DAG.getRegisterMask(TRI->getSMStartStopCallPreservedMask());
89288924
SDValue MSROp =
89298925
DAG.getTargetConstant((int32_t)AArch64SVCR::SVCRSM, DL, MVT::i32);
8930-
SDValue ConditionOp = DAG.getTargetConstant(Condition, DL, MVT::i64);
8931-
SmallVector<SDValue> Ops = {Chain, MSROp, ConditionOp};
8926+
SmallVector<SDValue> Ops = {Chain, MSROp};
8927+
unsigned Opcode;
89328928
if (Condition != AArch64SME::Always) {
8929+
SDValue ConditionOp = DAG.getTargetConstant(Condition, DL, MVT::i64);
8930+
Opcode = Enable ? AArch64ISD::COND_SMSTART : AArch64ISD::COND_SMSTOP;
89338931
assert(PStateSM && "PStateSM should be defined");
8932+
Ops.push_back(ConditionOp);
89348933
Ops.push_back(PStateSM);
8934+
} else {
8935+
Opcode = Enable ? AArch64ISD::SMSTART : AArch64ISD::SMSTOP;
89358936
}
89368937
Ops.push_back(RegMask);
89378938

89388939
if (InGlue)
89398940
Ops.push_back(InGlue);
89408941

8941-
unsigned Opcode = Enable ? AArch64ISD::SMSTART : AArch64ISD::SMSTOP;
89428942
return DAG.getNode(Opcode, DL, DAG.getVTList(MVT::Other, MVT::Glue), Ops);
89438943
}
89448944

@@ -9203,9 +9203,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
92039203

92049204
if (DisableZA)
92059205
Chain = DAG.getNode(
9206-
AArch64ISD::SMSTOP, DL, MVT::Other, Chain,
9207-
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
9208-
DAG.getConstant(AArch64SME::Always, DL, MVT::i64));
9206+
AArch64ISD::SMSTOP, DL, DAG.getVTList(MVT::Other, MVT::Glue), Chain,
9207+
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
92099208

92109209
// Adjust the stack pointer for the new arguments...
92119210
// These operations are automatically eliminated by the prolog/epilog pass
@@ -9682,9 +9681,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
96829681
if (CallAttrs.requiresEnablingZAAfterCall())
96839682
// Unconditionally resume ZA.
96849683
Result = DAG.getNode(
9685-
AArch64ISD::SMSTART, DL, MVT::Other, Result,
9686-
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
9687-
DAG.getConstant(AArch64SME::Always, DL, MVT::i64));
9684+
AArch64ISD::SMSTART, DL, DAG.getVTList(MVT::Other, MVT::Glue), Result,
9685+
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
96889686

96899687
if (ShouldPreserveZT0)
96909688
Result =

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,8 @@ enum NodeType : unsigned {
7373

7474
SMSTART,
7575
SMSTOP,
76+
COND_SMSTART,
77+
COND_SMSTOP,
7678
RESTORE_ZA,
7779
RESTORE_ZT,
7880
SAVE_ZT,
@@ -360,7 +362,6 @@ enum NodeType : unsigned {
360362
CTLZ_MERGE_PASSTHRU,
361363
CTPOP_MERGE_PASSTHRU,
362364
DUP_MERGE_PASSTHRU,
363-
INDEX_VECTOR,
364365

365366
// Cast between vectors of the same element type but differ in length.
366367
REINTERPRET_CAST,
@@ -378,11 +379,6 @@ enum NodeType : unsigned {
378379
LD1RQ_MERGE_ZERO,
379380
LD1RO_MERGE_ZERO,
380381

381-
// Structured loads.
382-
SVE_LD2_MERGE_ZERO,
383-
SVE_LD3_MERGE_ZERO,
384-
SVE_LD4_MERGE_ZERO,
385-
386382
// Unsigned gather loads.
387383
GLD1_MERGE_ZERO,
388384
GLD1_SCALED_MERGE_ZERO,

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Lines changed: 18 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -10,12 +10,20 @@
1010
//
1111
//===----------------------------------------------------------------------===//
1212

13-
def AArch64_smstart : SDNode<"AArch64ISD::SMSTART", SDTypeProfile<0, 2,
14-
[SDTCisInt<0>, SDTCisInt<0>]>,
13+
def AArch64_smstart : SDNode<"AArch64ISD::SMSTART", SDTypeProfile<0, 1,
14+
[SDTCisInt<0>]>,
1515
[SDNPHasChain, SDNPSideEffect, SDNPVariadic,
1616
SDNPOptInGlue, SDNPOutGlue]>;
17-
def AArch64_smstop : SDNode<"AArch64ISD::SMSTOP", SDTypeProfile<0, 2,
18-
[SDTCisInt<0>, SDTCisInt<0>]>,
17+
def AArch64_smstop : SDNode<"AArch64ISD::SMSTOP", SDTypeProfile<0, 1,
18+
[SDTCisInt<0>]>,
19+
[SDNPHasChain, SDNPSideEffect, SDNPVariadic,
20+
SDNPOptInGlue, SDNPOutGlue]>;
21+
def AArch64_cond_smstart : SDNode<"AArch64ISD::COND_SMSTART", SDTypeProfile<0, 3,
22+
[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>,
23+
[SDNPHasChain, SDNPSideEffect, SDNPVariadic,
24+
SDNPOptInGlue, SDNPOutGlue]>;
25+
def AArch64_cond_smstop : SDNode<"AArch64ISD::COND_SMSTOP", SDTypeProfile<0, 3,
26+
[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>,
1927
[SDNPHasChain, SDNPSideEffect, SDNPVariadic,
2028
SDNPOptInGlue, SDNPOutGlue]>;
2129
def AArch64_restore_za : SDNode<"AArch64ISD::RESTORE_ZA", SDTypeProfile<0, 3,
@@ -305,15 +313,15 @@ def MSRpstatePseudo :
305313
let Defs = [VG];
306314
}
307315

308-
def : Pat<(AArch64_smstart (i32 svcr_op:$pstate), (i64 timm0_31:$condition)),
309-
(MSRpstatePseudo svcr_op:$pstate, 0b1, timm0_31:$condition)>;
310-
def : Pat<(AArch64_smstop (i32 svcr_op:$pstate), (i64 timm0_31:$condition)),
311-
(MSRpstatePseudo svcr_op:$pstate, 0b0, timm0_31:$condition)>;
316+
def : Pat<(AArch64_cond_smstart (i32 svcr_op:$pstate), (i64 timm0_31:$condition), (i64 GPR64:$pstatesm)),
317+
(MSRpstatePseudo svcr_op:$pstate, 0b1, timm0_31:$condition, GPR64:$pstatesm)>;
318+
def : Pat<(AArch64_cond_smstop (i32 svcr_op:$pstate), (i64 timm0_31:$condition), (i64 GPR64:$pstatesm)),
319+
(MSRpstatePseudo svcr_op:$pstate, 0b0, timm0_31:$condition, GPR64:$pstatesm)>;
312320

313321
// Unconditional start/stop
314-
def : Pat<(AArch64_smstart (i32 svcr_op:$pstate), (i64 /*AArch64SME::Always*/0)),
322+
def : Pat<(AArch64_smstart (i32 svcr_op:$pstate)),
315323
(MSRpstatesvcrImm1 svcr_op:$pstate, 0b1)>;
316-
def : Pat<(AArch64_smstop (i32 svcr_op:$pstate), (i64 /*AArch64SME::Always*/0)),
324+
def : Pat<(AArch64_smstop (i32 svcr_op:$pstate)),
317325
(MSRpstatesvcrImm1 svcr_op:$pstate, 0b0)>;
318326

319327

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