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smanna12smanna12
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update new patch to align with spec
Signed-off-by: Soumi Manna <[email protected]>
1 parent c0cb1fe commit 7000c8e

36 files changed

+617
-656
lines changed

‎clang/include/clang/Basic/Attr.td

Lines changed: 27 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -1183,8 +1183,7 @@ def SYCLScope : Attr {
11831183
}
11841184

11851185
def SYCLDeviceIndirectlyCallable : InheritableAttr {
1186-
let Spellings = [ CXX11<"intel", "device_indirectly_callable">,
1187-
CXX11<"INTEL", "device_indirectly_callable"> ];
1186+
let Spellings = [ CXX11<"intel", "device_indirectly_callable">];
11881187
let Subjects = SubjectList<[Function]>;
11891188
let LangOpts = [SYCLIsDevice];
11901189
let Documentation = [SYCLDeviceIndirectlyCallableDocs];
@@ -1208,8 +1207,7 @@ def SYCLRequiresDecomposition : InheritableAttr {
12081207
}
12091208

12101209
def SYCLIntelKernelArgsRestrict : InheritableAttr {
1211-
let Spellings = [ CXX11<"intel", "kernel_args_restrict">,
1212-
CXX11<"INTEL", "kernel_args_restrict"> ];
1210+
let Spellings = [ CXX11<"intel", "kernel_args_restrict">];
12131211
let Subjects = SubjectList<[Function], ErrorDiag>;
12141212
let LangOpts = [ SYCLIsDevice, SYCLIsHost ];
12151213
let Documentation = [ SYCLIntelKernelArgsRestrictDocs ];
@@ -1219,7 +1217,7 @@ def SYCLIntelKernelArgsRestrict : InheritableAttr {
12191217

12201218
def SYCLIntelNumSimdWorkItems : InheritableAttr {
12211219
let Spellings = [CXX11<"intelfpga","num_simd_work_items">,
1222-
CXX11<"INTEL","num_simd_work_items">];
1220+
CXX11<"intel","num_simd_work_items">];
12231221
let Args = [ExprArgument<"Value">];
12241222
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12251223
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1229,7 +1227,7 @@ def SYCLIntelNumSimdWorkItems : InheritableAttr {
12291227

12301228
def SYCLIntelMaxWorkGroupSize : InheritableAttr {
12311229
let Spellings = [CXX11<"intelfpga","max_work_group_size">,
1232-
CXX11<"INTEL","max_work_group_size">];
1230+
CXX11<"intel","max_work_group_size">];
12331231
let Args = [UnsignedArgument<"XDim">,
12341232
UnsignedArgument<"YDim">,
12351233
UnsignedArgument<"ZDim">];
@@ -1241,7 +1239,7 @@ def SYCLIntelMaxWorkGroupSize : InheritableAttr {
12411239

12421240
def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
12431241
let Spellings = [CXX11<"intelfpga","max_global_work_dim">,
1244-
CXX11<"INTEL","max_global_work_dim">];
1242+
CXX11<"intel","max_global_work_dim">];
12451243
let Args = [UnsignedArgument<"Number">];
12461244
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12471245
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1251,7 +1249,7 @@ def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
12511249

12521250
def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
12531251
let Spellings = [CXX11<"intelfpga","no_global_work_offset">,
1254-
CXX11<"INTEL","no_global_work_offset">];
1252+
CXX11<"intel","no_global_work_offset">];
12551253
let Args = [BoolArgument<"Enabled", 1>];
12561254
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12571255
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1313,8 +1311,7 @@ def LoopUnrollHint : InheritableAttr {
13131311

13141312
def IntelReqdSubGroupSize: InheritableAttr {
13151313
let Spellings = [GNU<"intel_reqd_sub_group_size">,
1316-
CXX11<"intel", "reqd_sub_group_size">,
1317-
CXX11<"INTEL", "reqd_sub_group_size">];
1314+
CXX11<"intel", "reqd_sub_group_size">];
13181315
let Args = [ExprArgument<"Value">];
13191316
let Subjects = SubjectList<[Function, CXXMethod], ErrorDiag>;
13201317
let Documentation = [IntelReqdSubGroupSizeDocs];
@@ -1694,7 +1691,7 @@ def Mode : Attr {
16941691

16951692
def SYCLIntelFPGAIVDep : Attr {
16961693
let Spellings = [CXX11<"intelfpga","ivdep">,
1697-
CXX11<"INTEL","ivdep">];
1694+
CXX11<"intel","ivdep">];
16981695
let Args = [
16991696
ExprArgument<"SafelenExpr">, ExprArgument<"ArrayExpr">,
17001697
UnsignedArgument<"SafelenValue">
@@ -1741,7 +1738,7 @@ def SYCLIntelFPGAIVDep : Attr {
17411738

17421739
def SYCLIntelFPGAII : Attr {
17431740
let Spellings = [CXX11<"intelfpga","ii">,
1744-
CXX11<"INTEL","ii">];
1741+
CXX11<"intel","ii">];
17451742
let Args = [ExprArgument<"IntervalExpr">];
17461743
let LangOpts = [SYCLIsDevice, SYCLIsHost];
17471744
let HasCustomTypeTransform = 1;
@@ -1755,7 +1752,7 @@ def SYCLIntelFPGAII : Attr {
17551752

17561753
def SYCLIntelFPGAMaxConcurrency : Attr {
17571754
let Spellings = [CXX11<"intelfpga","max_concurrency">,
1758-
CXX11<"INTEL","max_concurrency">];
1755+
CXX11<"intel","max_concurrency">];
17591756
let Args = [ExprArgument<"NThreadsExpr">];
17601757
let LangOpts = [SYCLIsDevice, SYCLIsHost];
17611758
let HasCustomTypeTransform = 1;
@@ -1769,7 +1766,7 @@ def SYCLIntelFPGAMaxConcurrency : Attr {
17691766

17701767
def SYCLIntelFPGALoopCoalesce : Attr {
17711768
let Spellings = [CXX11<"intelfpga","loop_coalesce">,
1772-
CXX11<"INTEL","loop_coalesce">];
1769+
CXX11<"intel","loop_coalesce">];
17731770
let Args = [ExprArgument<"NExpr">];
17741771
let LangOpts = [SYCLIsDevice, SYCLIsHost];
17751772
let HasCustomTypeTransform = 1;
@@ -1783,7 +1780,7 @@ def SYCLIntelFPGALoopCoalesce : Attr {
17831780

17841781
def SYCLIntelFPGADisableLoopPipelining : Attr {
17851782
let Spellings = [CXX11<"intelfpga","disable_loop_pipelining">,
1786-
CXX11<"INTEL","disable_loop_pipelining">];
1783+
CXX11<"intel","disable_loop_pipelining">];
17871784
let LangOpts = [SYCLIsDevice, SYCLIsHost];
17881785
let HasCustomTypeTransform = 1;
17891786
let AdditionalMembers = [{
@@ -1796,7 +1793,7 @@ def SYCLIntelFPGADisableLoopPipelining : Attr {
17961793

17971794
def SYCLIntelFPGAMaxInterleaving : Attr {
17981795
let Spellings = [CXX11<"intelfpga","max_interleaving">,
1799-
CXX11<"INTEL","max_interleaving">];
1796+
CXX11<"intel","max_interleaving">];
18001797
let Args = [ExprArgument<"NExpr">];
18011798
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18021799
let HasCustomTypeTransform = 1;
@@ -1810,7 +1807,7 @@ def SYCLIntelFPGAMaxInterleaving : Attr {
18101807

18111808
def SYCLIntelFPGASpeculatedIterations : Attr {
18121809
let Spellings = [CXX11<"intelfpga","speculated_iterations">,
1813-
CXX11<"INTEL","speculated_iterations">];
1810+
CXX11<"intel","speculated_iterations">];
18141811
let Args = [ExprArgument<"NExpr">];
18151812
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18161813
let HasCustomTypeTransform = 1;
@@ -1856,7 +1853,7 @@ def IntelFPGALocalOrStaticVar : SubsetSubject<Var,
18561853

18571854
def IntelFPGADoublePump : Attr {
18581855
let Spellings = [CXX11<"intelfpga", "doublepump">,
1859-
CXX11<"INTEL", "doublepump">];
1856+
CXX11<"intel", "doublepump">];
18601857
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
18611858
Field], ErrorDiag>;
18621859
let LangOpts = [SYCLIsDevice, SYCLIsHost];
@@ -1865,7 +1862,7 @@ def IntelFPGADoublePump : Attr {
18651862

18661863
def IntelFPGASinglePump : Attr {
18671864
let Spellings = [CXX11<"intelfpga", "singlepump">,
1868-
CXX11<"INTEL", "singlepump">];
1865+
CXX11<"intel", "singlepump">];
18691866
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
18701867
Field], ErrorDiag>;
18711868
let LangOpts = [SYCLIsDevice, SYCLIsHost];
@@ -1874,7 +1871,7 @@ def IntelFPGASinglePump : Attr {
18741871

18751872
def IntelFPGAMemory : Attr {
18761873
let Spellings = [CXX11<"intelfpga", "memory">,
1877-
CXX11<"INTEL", "fpga_memory">];
1874+
CXX11<"intel", "fpga_memory">];
18781875
let Args = [EnumArgument<"Kind", "MemoryKind",
18791876
["MLAB", "BLOCK_RAM", ""],
18801877
["MLAB", "BlockRAM", "Default"], 1>];
@@ -1895,7 +1892,7 @@ def IntelFPGAMemory : Attr {
18951892

18961893
def IntelFPGARegister : Attr {
18971894
let Spellings = [CXX11<"intelfpga", "register">,
1898-
CXX11<"INTEL", "fpga_register">];
1895+
CXX11<"intel", "fpga_register">];
18991896
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19001897
Field], ErrorDiag>;
19011898
let LangOpts = [SYCLIsDevice, SYCLIsHost];
@@ -1905,7 +1902,7 @@ def IntelFPGARegister : Attr {
19051902
// One integral argument.
19061903
def IntelFPGABankWidth : Attr {
19071904
let Spellings = [CXX11<"intelfpga","bankwidth">,
1908-
CXX11<"INTEL","bankwidth">];
1905+
CXX11<"intel","bankwidth">];
19091906
let Args = [ExprArgument<"Value">];
19101907
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19111908
Field], ErrorDiag>;
@@ -1923,7 +1920,7 @@ def IntelFPGABankWidth : Attr {
19231920

19241921
def IntelFPGANumBanks : Attr {
19251922
let Spellings = [CXX11<"intelfpga","numbanks">,
1926-
CXX11<"INTEL","numbanks">];
1923+
CXX11<"intel","numbanks">];
19271924
let Args = [ExprArgument<"Value">];
19281925
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19291926
Field], ErrorDiag>;
@@ -1941,7 +1938,7 @@ def IntelFPGANumBanks : Attr {
19411938

19421939
def IntelFPGAPrivateCopies : InheritableAttr {
19431940
let Spellings = [CXX11<"intelfpga","private_copies">,
1944-
CXX11<"INTEL","private_copies">];
1941+
CXX11<"intel","private_copies">];
19451942
let Args = [ExprArgument<"Value">];
19461943
let LangOpts = [SYCLIsDevice, SYCLIsHost];
19471944
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
@@ -1959,7 +1956,7 @@ def IntelFPGAPrivateCopies : InheritableAttr {
19591956
// Two string arguments.
19601957
def IntelFPGAMerge : Attr {
19611958
let Spellings = [CXX11<"intelfpga","merge">,
1962-
CXX11<"INTEL","merge">];
1959+
CXX11<"intel","merge">];
19631960
let Args = [StringArgument<"Name">, StringArgument<"Direction">];
19641961
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19651962
Field], ErrorDiag>;
@@ -1969,7 +1966,7 @@ def IntelFPGAMerge : Attr {
19691966

19701967
def IntelFPGAMaxReplicates : Attr {
19711968
let Spellings = [CXX11<"intelfpga","max_replicates">,
1972-
CXX11<"INTEL","max_replicates">];
1969+
CXX11<"intel","max_replicates">];
19731970
let Args = [ExprArgument<"Value">];
19741971
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19751972
Field], ErrorDiag>;
@@ -1987,7 +1984,7 @@ def IntelFPGAMaxReplicates : Attr {
19871984

19881985
def IntelFPGASimpleDualPort : Attr {
19891986
let Spellings = [CXX11<"intelfpga","simple_dual_port">,
1990-
CXX11<"INTEL","simple_dual_port">];
1987+
CXX11<"intel","simple_dual_port">];
19911988
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19921989
Field], ErrorDiag>;
19931990
let LangOpts = [SYCLIsDevice, SYCLIsHost];
@@ -2013,7 +2010,7 @@ def SYCLIntelPipeIO : Attr {
20132010
// Variadic integral arguments.
20142011
def IntelFPGABankBits : Attr {
20152012
let Spellings = [CXX11<"intelfpga", "bank_bits">,
2016-
CXX11<"INTEL", "bank_bits">];
2013+
CXX11<"intel", "bank_bits">];
20172014
let Args = [VariadicExprArgument<"Args">];
20182015
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20192016
Field], ErrorDiag>;
@@ -2031,7 +2028,7 @@ def IntelFPGABankBits : Attr {
20312028

20322029
def IntelFPGAForcePow2Depth : Attr {
20332030
let Spellings = [CXX11<"intelfpga","force_pow2_depth">,
2034-
CXX11<"INTEL","force_pow2_depth">];
2031+
CXX11<"intel","force_pow2_depth">];
20352032
let Args = [ExprArgument<"Value">];
20362033
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20372034
Field], ErrorDiag>;
@@ -2651,8 +2648,7 @@ def NoDeref : TypeAttr {
26512648
def ReqdWorkGroupSize : InheritableAttr {
26522649
let Spellings = [GNU<"reqd_work_group_size">,
26532650
CXX11<"intel","reqd_work_group_size">,
2654-
CXX11<"cl","reqd_work_group_size">,
2655-
CXX11<"INTEL","reqd_work_group_size">];
2651+
CXX11<"cl","reqd_work_group_size">];
26562652
let Args = [UnsignedArgument<"XDim">, DefaultUnsignedArgument<"YDim", 1>,
26572653
DefaultUnsignedArgument<"ZDim", 1>];
26582654
let Subjects = SubjectList<[Function], ErrorDiag>;

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