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[SYCL][FPGA] Add AST tests for loop attributes (#11428)
This patch adds AST tests which we did not have before for the FPGA Loop Attributes below: 1. [[intel::max_interleaving()]] 2. [[intel::loop_coalesce]] 3. [[intel::max_concurrency()]] 4. [[intel::initiation_interval()]], 5. [[intel::speculated_iterations()]]. --------- Signed-off-by: Soumi Manna <[email protected]>
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‎clang/test/SemaSYCL/intel-fpga-enable-loop-pipelining-ast.cpp

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‎clang/test/SemaSYCL/intel-fpga-loop-ast.cpp

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// RUN: %clang_cc1 -fsycl-is-device -internal-isystem %S/Inputs -Wno-sycl-2017-compat -ast-dump %s | FileCheck %s
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// Add AST tests for Loop attributes: [[intel::enable_loop_pipelining]],
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// [[intel::max_interleaving()]], [[intel::loop_coalesce]],
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// [[intel::max_concurrency()]], [[intel::initiation_interval()]],
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// and [[intel::speculated_iterations()]].
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#include "sycl.hpp"
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using namespace sycl;
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queue q;
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void fpga_enable_loop_pipelining() {
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int a1[10], a2[10];
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelEnableLoopPipeliningAttr
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[[intel::enable_loop_pipelining]] for (int p = 0; p < 10; ++p) {
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a1[p] = a2[p] = 0;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelEnableLoopPipeliningAttr
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int i = 0;
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[[intel::enable_loop_pipelining]] while (i < 10) {
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a1[i] += 3;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelEnableLoopPipeliningAttr
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for (int i = 0; i < 10; ++i) {
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[[intel::enable_loop_pipelining]] for (int j = 0; j < 10; ++j) {
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a1[i] += a1[j];
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}
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelEnableLoopPipeliningAttr
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int b = 10;
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[[intel::enable_loop_pipelining]] do {
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b = b + 1;
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} while (b < 20);
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelEnableLoopPipeliningAttr
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int c[] = {0, 1, 2, 3, 4, 5};
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[[intel::enable_loop_pipelining]] for (int n : c) { n *= 2; }
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}
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void fpga_max_concurrency() {
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int a1[10], a2[10];
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelMaxConcurrencyAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 0
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 0
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[[intel::max_concurrency(0)]] for (int p = 0; p < 10; ++p) {
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a1[p] = a2[p] = 0;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelMaxConcurrencyAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 4
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 4
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int i = 0;
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[[intel::max_concurrency(4)]] while (i < 10) {
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a1[i] += 3;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelMaxConcurrencyAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 8
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 8
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for (int i = 0; i < 10; ++i) {
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[[intel::max_concurrency(8)]] for (int j = 0; j < 10; ++j) {
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a1[i] += a1[j];
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}
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelMaxConcurrencyAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 12
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 12
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int b = 10;
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[[intel::max_concurrency(12)]] do {
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b = b + 1;
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} while (b < 20);
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelMaxConcurrencyAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 16
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 16
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int c[] = {0, 1, 2, 3, 4, 5};
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[[intel::max_concurrency(16)]] for (int n : c) { n *= 2; }
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}
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void fpga_max_interleaving() {
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int a1[10], a2[10];
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelMaxInterleavingAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 0
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 0
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[[intel::max_interleaving(0)]] for (int p = 0; p < 10; ++p) {
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a1[p] = a2[p] = 0;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelMaxInterleavingAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 1
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 1
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int i = 0;
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[[intel::max_interleaving(1)]] while (i < 10) {
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a1[i] += 3;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelMaxInterleavingAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 1
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 1
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for (int i = 0; i < 10; ++i) {
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[[intel::max_interleaving(1)]] for (int j = 0; j < 10; ++j) {
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a1[i] += a1[j];
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}
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelMaxInterleavingAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 0
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 0
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int b = 10;
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[[intel::max_interleaving(0)]] do {
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b = b + 1;
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} while (b < 20);
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelMaxInterleavingAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 1
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 1
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int c[] = {0, 1, 2, 3, 4, 5};
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[[intel::max_interleaving(1)]] for (int n : c) { n *= 2; }
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}
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void fpga_speculated_iterations() {
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int a1[10], a2[10];
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelSpeculatedIterationsAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 0
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 0
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[[intel::speculated_iterations(0)]] for (int p = 0; p < 10; ++p) {
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a1[p] = a2[p] = 0;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelSpeculatedIterationsAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 12
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 12
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int i = 0;
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[[intel::speculated_iterations(12)]] while (i < 10) {
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a1[i] += 3;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelSpeculatedIterationsAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 16
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 16
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for (int i = 0; i < 10; ++i) {
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[[intel::speculated_iterations(16)]] for (int j = 0; j < 10; ++j) {
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a1[i] += a1[j];
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}
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelSpeculatedIterationsAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 8
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 8
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int b = 10;
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[[intel::speculated_iterations(8)]] do {
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b = b + 1;
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} while (b < 20);
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelSpeculatedIterationsAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 22
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 22
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int c[] = {0, 1, 2, 3, 4, 5};
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[[intel::speculated_iterations(22)]] for (int n : c) { n *= 2; }
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}
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void fpga_initiation_interval() {
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int a1[10], a2[10];
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelInitiationIntervalAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 10
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 10
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[[intel::initiation_interval(10)]] for (int p = 0; p < 10; ++p) {
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a1[p] = a2[p] = 0;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelInitiationIntervalAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 12
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 12
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int i = 0;
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[[intel::initiation_interval(12)]] while (i < 10) {
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a1[i] += 3;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelInitiationIntervalAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 16
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 16
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for (int i = 0; i < 10; ++i) {
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[[intel::initiation_interval(16)]] for (int j = 0; j < 10; ++j) {
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a1[i] += a1[j];
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}
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelInitiationIntervalAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 8
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 8
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int b = 10;
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[[intel::initiation_interval(8)]] do {
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b = b + 1;
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} while (b < 20);
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelInitiationIntervalAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 22
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 22
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int c[] = {0, 1, 2, 3, 4, 5};
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[[intel::initiation_interval(22)]] for (int n : c) { n *= 2; }
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}
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void fpga_loop_coalesce() {
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int a1[10], a2[10];
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelLoopCoalesceAttr
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[[intel::loop_coalesce]] for (int p = 0; p < 10; ++p) {
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a1[p] = a2[p] = 0;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelLoopCoalesceAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 12
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 12
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int i = 0;
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[[intel::loop_coalesce(12)]] while (i < 10) {
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a1[i] += 3;
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelLoopCoalesceAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 16
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 16
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for (int i = 0; i < 10; ++i) {
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[[intel::loop_coalesce(16)]] for (int j = 0; j < 10; ++j) {
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a1[i] += a1[j];
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}
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}
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelLoopCoalesceAttr
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int b = 10;
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[[intel::loop_coalesce]] do {
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b = b + 1;
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} while (b < 20);
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// CHECK: AttributedStmt
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// CHECK-NEXT: SYCLIntelLoopCoalesceAttr
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// CHECK-NEXT: ConstantExpr{{.*}}'int'
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// CHECK-NEXT: value: Int 22
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// CHECK-NEXT: IntegerLiteral {{.*}} 'int' 22
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int c[] = {0, 1, 2, 3, 4, 5};
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[[intel::loop_coalesce(22)]] for (int n : c) { n *= 2; }
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}
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void foo() {
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q.submit([&](handler &h) {
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h.single_task<class kernel_function>([]() {
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fpga_enable_loop_pipelining();
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fpga_max_concurrency();
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fpga_max_interleaving();
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fpga_speculated_iterations();
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fpga_initiation_interval();
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fpga_loop_coalesce();
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});
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});
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}

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