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mlychkov
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Translate Intel FPGA force_pow2_depth memory attribute
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_attributes.asciidoc Signed-off-by: Mikhail Lychkov <[email protected]
1 parent c9b637a commit 73dd705

10 files changed

+197
-6
lines changed

‎llvm-spirv/lib/SPIRV/SPIRVReader.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2956,6 +2956,8 @@ void generateIntelFPGAAnnotation(const SPIRVEntry *E,
29562956
Out << Literals[I] << ",";
29572957
Out << Literals.back() << '}';
29582958
}
2959+
if (E->hasDecorate(DecorationForcePow2DepthINTEL, 0, &Result))
2960+
Out << "{force_pow2_depth:" << Result << '}';
29592961
if (E->hasDecorate(DecorationUserSemantic))
29602962
Out << E->getDecorationStringLiteral(DecorationUserSemantic).front();
29612963
}
@@ -3005,6 +3007,9 @@ void generateIntelFPGAAnnotationForStructMember(
30053007
Out << Literals[I] << ",";
30063008
Out << Literals.back() << '}';
30073009
}
3010+
if (E->hasMemberDecorate(DecorationForcePow2DepthINTEL, 0, MemberNumber,
3011+
&Result))
3012+
Out << "{force_pow2_depth:" << Result << '}';
30083013

30093014
if (E->hasMemberDecorate(DecorationUserSemantic, 0, MemberNumber))
30103015
Out << E->getMemberDecorationStringLiteral(DecorationUserSemantic,

‎llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1432,6 +1432,7 @@ tryParseIntelFPGAAnnotationString(StringRef AnnotatedCode) {
14321432
.Case("max_replicates", DecorationMaxReplicatesINTEL)
14331433
.Case("bank_bits", DecorationBankBitsINTEL)
14341434
.Case("merge", DecorationMergeINTEL)
1435+
.Case("force_pow2_depth", DecorationForcePow2DepthINTEL)
14351436
.Default(DecorationUserSemantic);
14361437
if (Dec == DecorationUserSemantic)
14371438
Value = AnnotatedCode.substr(From, To + 1);
@@ -1499,6 +1500,7 @@ void addIntelFPGADecorations(
14991500
// DecorationBankwidthINTEL
15001501
// DecorationMaxPrivateCopiesINTEL
15011502
// DecorationMaxReplicatesINTEL
1503+
// DecorationForcePow2DepthINTEL
15021504
default:
15031505
SPIRVWord Result = 0;
15041506
StringRef(I.second).getAsInteger(10, Result);
@@ -1553,6 +1555,7 @@ void addIntelFPGADecorationsForStructMember(
15531555
// DecorationBankwidthINTEL
15541556
// DecorationMaxPrivateCopiesINTEL
15551557
// DecorationMaxReplicatesINTEL
1558+
// DecorationForcePow2DepthINTEL
15561559
default:
15571560
SPIRVWord Result = 0;
15581561
StringRef(I.second).getAsInteger(10, Result);

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVDecorate.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -153,6 +153,7 @@ class SPIRVDecorate : public SPIRVDecorateGeneric {
153153
case DecorationSimpleDualPortINTEL:
154154
case DecorationMergeINTEL:
155155
case DecorationBankBitsINTEL:
156+
case DecorationForcePow2DepthINTEL:
156157
return getSet(ExtensionID::SPV_INTEL_fpga_memory_attributes);
157158
case DecorationReferencedIndirectlyINTEL:
158159
return getSet(ExtensionID::SPV_INTEL_function_pointers);
@@ -252,6 +253,7 @@ class SPIRVMemberDecorate : public SPIRVDecorateGeneric {
252253
case DecorationSimpleDualPortINTEL:
253254
case DecorationMergeINTEL:
254255
case DecorationBankBitsINTEL:
256+
case DecorationForcePow2DepthINTEL:
255257
return getSet(ExtensionID::SPV_INTEL_fpga_memory_attributes);
256258
case DecorationIOPipeStorageINTEL:
257259
return getSet(ExtensionID::SPV_INTEL_io_pipes);

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -363,6 +363,8 @@ template <> inline void SPIRVMap<Decoration, SPIRVCapVec>::init() {
363363
{CapabilityFPGAMemoryAttributesINTEL});
364364
ADD_VEC_INIT(DecorationMergeINTEL, {CapabilityFPGAMemoryAttributesINTEL});
365365
ADD_VEC_INIT(DecorationBankBitsINTEL, {CapabilityFPGAMemoryAttributesINTEL});
366+
ADD_VEC_INIT(DecorationForcePow2DepthINTEL,
367+
{CapabilityFPGAMemoryAttributesINTEL});
366368
ADD_VEC_INIT(DecorationReferencedIndirectlyINTEL,
367369
{CapabilityIndirectReferencesINTEL});
368370
ADD_VEC_INIT(DecorationIOPipeStorageINTEL, {CapabilityIOPipeINTEL});

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -410,6 +410,7 @@ inline bool isValid(spv::Decoration V) {
410410
case DecorationSinglepumpINTEL:
411411
case DecorationDoublepumpINTEL:
412412
case DecorationBankBitsINTEL:
413+
case DecorationForcePow2DepthINTEL:
413414
case DecorationReferencedIndirectlyINTEL:
414415
return true;
415416
default:

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -348,6 +348,7 @@ template <> inline void SPIRVMap<Decoration, std::string>::init() {
348348
add(DecorationSimpleDualPortINTEL, "SimpleDualPortINTEL");
349349
add(DecorationMergeINTEL, "MergeINTEL");
350350
add(DecorationBankBitsINTEL, "BankBitsINTEL");
351+
add(DecorationForcePow2DepthINTEL, "ForcePow2DepthINTEL");
351352
add(DecorationReferencedIndirectlyINTEL, "ReferencedIndirectlyINTEL");
352353
add(DecorationIOPipeStorageINTEL, "IOPipeStorageINTEL");
353354
}

‎llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -406,6 +406,7 @@ enum Decoration {
406406
DecorationSimpleDualPortINTEL = 5833,
407407
DecorationMergeINTEL = 5834,
408408
DecorationBankBitsINTEL = 5835,
409+
DecorationForcePow2DepthINTEL = 5836,
409410
DecorationIOPipeStorageINTEL = 5944,
410411
DecorationMax = 0x7fffffff,
411412
};

‎llvm-spirv/test/IntelFPGAMemoryAttributes.ll

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -150,6 +150,25 @@
150150
; s.field = 0;
151151
; }
152152
;
153+
; void force_pow2_depth_attr() {
154+
; [[intelfpga::force_pow2_depth(0)]] int fp2d_var;
155+
;
156+
; [[intelfpga::force_pow2_depth(1)]] struct fp2d_st {
157+
; int field;
158+
; } s;
159+
; s.field = 0;
160+
; }
161+
;
162+
; template <int A>
163+
; void templ_force_pow2_depth_attr() {
164+
; [[intelfpga::force_pow2_depth(A)]] int templ_fp2d_var;
165+
;
166+
; [[intelfpga::force_pow2_depth(A)]] struct templ_fp2d_st {
167+
; int field;
168+
; } s;
169+
; s.field = 0;
170+
; }
171+
;
153172
; template <typename name, typename Func>
154173
; __attribute__((sycl_kernel)) void kernel_single_task(Func kernelFunc) {
155174
; kernelFunc();
@@ -173,6 +192,8 @@
173192
; simple_dual_port_attr();
174193
; bank_bits_attr();
175194
; templ_bank_bits_attr<4, 5>();
195+
; force_pow2_depth_attr();
196+
; templ_force_pow2_depth_attr<1>();
176197
; });
177198
; return 0;
178199
; }
@@ -205,6 +226,7 @@
205226
; CHECK-SPIRV: Decorate {{[0-9]+}} DoublepumpINTEL
206227
; CHECK-SPIRV: Decorate {{[0-9]+}} MaxReplicatesINTEL 8
207228
; CHECK-SPIRV: Decorate {{[0-9]+}} SimpleDualPortINTEL
229+
; CHECK-SPIRV: Decorate {{[0-9]+}} ForcePow2DepthINTEL 1
208230
; CHECK-SPIRV: Decorate {{[0-9]+}} MemoryINTEL "MLAB"
209231
; CHECK-SPIRV: Decorate {{[0-9]+}} MemoryINTEL "BLOCK_RAM"
210232
; CHECK-SPIRV: Decorate {{[0-9]+}} NumbanksINTEL 8
@@ -221,6 +243,7 @@
221243
; CHECK-SPIRV: Decorate {{[0-9]+}} BankBitsINTEL 5
222244
; CHECK-SPIRV: Decorate {{[0-9]+}} BankBitsINTEL 4 5
223245
; CHECK-SPIRV: Decorate {{[0-9]+}} BankBitsINTEL 2 1 0
246+
; CHECK-SPIRV: Decorate {{[0-9]+}} ForcePow2DepthINTEL 0
224247

225248
target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
226249
target triple = "spir"
@@ -242,6 +265,8 @@ target triple = "spir"
242265
%struct.simple_dual_port_st = type { i32 }
243266
%struct.bank_bits_st = type { i32 }
244267
%struct.templ_bank_bits_st = type { i32 }
268+
%struct.fp2d_st = type { i32 }
269+
%struct.templ_fp2d_st = type { i32 }
245270

246271
; CHECK-LLVM: [[STR_NMB_VAR:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:16}
247272
; CHECK-LLVM: [[STR_NMB_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:2}
@@ -275,6 +300,10 @@ target triple = "spir"
275300
; CHECK-LLVM: [[STR_BBT_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:2}{bank_bits:2}
276301
; CHECK-LLVM: [[STR_BBT_TE1:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:4}{bank_bits:4,5}
277302
; CHECK-LLVM: [[STR_BBT_TE2:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:2}{bank_bits:5}
303+
; CHECK-LLVM: [[STR_FP2_VAR:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{force_pow2_depth:0}
304+
; CHECK-LLVM: [[STR_FP2_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{force_pow2_depth:1}
305+
; CHECK-LLVM: [[STR_FP2_TE1:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{force_pow2_depth:1}
306+
; CHECK-LLVM: [[STR_FP2_TE2:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{force_pow2_depth:1}
278307
@.str = private unnamed_addr constant [42 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:16}\00", section "llvm.metadata"
279308
@.str.1 = private unnamed_addr constant [25 x i8] c"intel-fpga-local-var.cpp\00", section "llvm.metadata"
280309
@.str.2 = private unnamed_addr constant [41 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:2}\00", section "llvm.metadata"
@@ -300,6 +329,8 @@ target triple = "spir"
300329
@.str.22 = private unnamed_addr constant [54 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:2}{bank_bits:2}\00", section "llvm.metadata"
301330
@.str.23 = private unnamed_addr constant [56 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:4}{bank_bits:4,5}\00", section "llvm.metadata"
302331
@.str.24 = private unnamed_addr constant [54 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:2}{bank_bits:5}\00", section "llvm.metadata"
332+
@.str.25 = private unnamed_addr constant [49 x i8] c"{memory:DEFAULT}{sizeinfo:4}{force_pow2_depth:0}\00", section "llvm.metadata"
333+
@.str.26 = private unnamed_addr constant [49 x i8] c"{memory:DEFAULT}{sizeinfo:4}{force_pow2_depth:1}\00", section "llvm.metadata"
303334

304335
; Function Attrs: norecurse nounwind
305336
define spir_kernel void @_ZTSZ4mainE15kernel_function() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 {
@@ -338,6 +369,8 @@ entry:
338369
call spir_func void @_Z21simple_dual_port_attrv()
339370
call spir_func void @_Z14bank_bits_attrv()
340371
call spir_func void @_Z20templ_bank_bits_attrILi4ELi5EEvv()
372+
call spir_func void @_Z21force_pow2_depth_attrv()
373+
call spir_func void @_Z27templ_force_pow2_depth_attrILi1EEvv()
341374
ret void
342375
}
343376

@@ -733,6 +766,54 @@ entry:
733766
ret void
734767
}
735768

769+
; Function Attrs: norecurse nounwind
770+
define spir_func void @_Z21force_pow2_depth_attrv() #3 {
771+
entry:
772+
%fp2d_var = alloca i32, align 4
773+
%s = alloca %struct.fp2d_st, align 4
774+
%0 = bitcast i32* %fp2d_var to i8*
775+
call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5
776+
%fp2d_var1 = bitcast i32* %fp2d_var to i8*
777+
; CHECK-LLVM: call void @llvm.var.annotation(i8* %{{[a-zA-Z0-9_]+}}, i8* getelementptr inbounds ([{{[0-9]+}} x i8], [{{[0-9]+}} x i8]* [[STR_FP2_VAR]], i32 0, i32 0), i8* undef, i32 undef)
778+
call void @llvm.var.annotation(i8* %fp2d_var1, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str.25, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str.1, i32 0, i32 0), i32 151)
779+
%1 = bitcast %struct.fp2d_st* %s to i8*
780+
call void @llvm.lifetime.start.p0i8(i64 4, i8* %1) #5
781+
%s2 = bitcast %struct.fp2d_st* %s to i8*
782+
; CHECK-LLVM: call void @llvm.var.annotation(i8* %{{[a-zA-Z0-9_]+}}, i8* getelementptr inbounds ([{{[0-9]+}} x i8], [{{[0-9]+}} x i8]* [[STR_FP2_SCT]], i32 0, i32 0), i8* undef, i32 undef)
783+
call void @llvm.var.annotation(i8* %s2, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str.26, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str.1, i32 0, i32 0), i32 155)
784+
%field = getelementptr inbounds %struct.fp2d_st, %struct.fp2d_st* %s, i32 0, i32 0
785+
store i32 0, i32* %field, align 4, !tbaa !41
786+
%2 = bitcast %struct.fp2d_st* %s to i8*
787+
call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5
788+
%3 = bitcast i32* %fp2d_var to i8*
789+
call void @llvm.lifetime.end.p0i8(i64 4, i8* %3) #5
790+
ret void
791+
}
792+
793+
; Function Attrs: norecurse nounwind
794+
define linkonce_odr spir_func void @_Z27templ_force_pow2_depth_attrILi1EEvv() #3 {
795+
entry:
796+
%templ_fp2d_var = alloca i32, align 4
797+
%s = alloca %struct.templ_fp2d_st, align 4
798+
%0 = bitcast i32* %templ_fp2d_var to i8*
799+
call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5
800+
%templ_fp2d_var1 = bitcast i32* %templ_fp2d_var to i8*
801+
; CHECK-LLVM: call void @llvm.var.annotation(i8* %{{[a-zA-Z0-9_]+}}, i8* getelementptr inbounds ([{{[0-9]+}} x i8], [{{[0-9]+}} x i8]* [[STR_FP2_TE1]], i32 0, i32 0), i8* undef, i32 undef)
802+
call void @llvm.var.annotation(i8* %templ_fp2d_var1, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str.26, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str.1, i32 0, i32 0), i32 161)
803+
%1 = bitcast %struct.templ_fp2d_st* %s to i8*
804+
call void @llvm.lifetime.start.p0i8(i64 4, i8* %1) #5
805+
%s2 = bitcast %struct.templ_fp2d_st* %s to i8*
806+
; CHECK-LLVM: call void @llvm.var.annotation(i8* %{{[a-zA-Z0-9_]+}}, i8* getelementptr inbounds ([{{[0-9]+}} x i8], [{{[0-9]+}} x i8]* [[STR_FP2_TE2]], i32 0, i32 0), i8* undef, i32 undef)
807+
call void @llvm.var.annotation(i8* %s2, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str.26, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str.1, i32 0, i32 0), i32 165)
808+
%field = getelementptr inbounds %struct.templ_fp2d_st, %struct.templ_fp2d_st* %s, i32 0, i32 0
809+
store i32 0, i32* %field, align 4, !tbaa !43
810+
%2 = bitcast %struct.templ_fp2d_st* %s to i8*
811+
call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5
812+
%3 = bitcast i32* %templ_fp2d_var to i8*
813+
call void @llvm.lifetime.end.p0i8(i64 4, i8* %3) #5
814+
ret void
815+
}
816+
736817
attributes #0 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "sycl-module-id"="intel-fpga-local-var.cpp" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
737818
attributes #1 = { argmemonly nounwind willreturn }
738819
attributes #2 = { inlinehint norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
@@ -786,3 +867,7 @@ attributes #5 = { nounwind }
786867
!38 = !{!"_ZTSZ14bank_bits_attrvE12bank_bits_st", !11, i64 0}
787868
!39 = !{!40, !11, i64 0}
788869
!40 = !{!"_ZTSZ20templ_bank_bits_attrILi4ELi5EEvvE18templ_bank_bits_st", !11, i64 0}
870+
!41 = !{!42, !11, i64 0}
871+
!42 = !{!"_ZTSZ21force_pow2_depth_attrvE7fp2d_st", !11, i64 0}
872+
!43 = !{!44, !11, i64 0}
873+
!44 = !{!"_ZTSZ27templ_force_pow2_depth_attrILi1EEvvE13templ_fp2d_st", !11, i64 0}

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