@@ -865,6 +865,83 @@ void SYCL::fpga::BackendCompiler::ConstructJob(
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C.addCommand (std::move (Cmd));
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}
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+ struct OclocInfo {
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+ const char *DeviceName;
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+ const char *PackageName;
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+ const char *Version;
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+ SmallVector<int , 8 > HexValues;
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+ };
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+
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+ // The PVCDevices data structure is organized by device name, with the
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+ // corresponding ocloc split release, version and possible Hex representations
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+ // of various PVC devices. This information is gathered from the following:
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+ // https://github.com/intel/compute-runtime/blob/master/shared/source/dll/devices/devices_base.inl
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+ // https://github.com/intel/compute-runtime/blob/master/shared/source/dll/devices/devices_additional.inl
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+ static OclocInfo PVCDevices[] = {
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+ {" pvc-sdv" , " gen12+" , " 12.60.1" , {}},
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+ {" pvc" ,
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+ " gen12+" ,
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+ " 12.60.7" ,
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+ {0x0BD0 , 0x0BD5 , 0x0BD6 , 0x0BD7 , 0x0BD8 , 0x0BD9 , 0x0BDA , 0x0BDB }}};
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+
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+ // Determine if any of the given arguments contain any PVC based values for
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+ // the -device option.
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+ static bool hasPVCDevice (const ArgStringList &CmdArgs) {
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+ bool DeviceSeen = false ;
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+ StringRef DeviceArg;
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+ for (StringRef Arg : CmdArgs) {
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+ // -device <arg> comes in as a single arg, split up all potential space
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+ // separated values.
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+ SmallVector<StringRef> SplitArgs;
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+ Arg.split (SplitArgs, ' ' );
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+ for (StringRef SplitArg : SplitArgs) {
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+ if (DeviceSeen) {
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+ DeviceArg = SplitArg;
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+ break ;
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+ }
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+ if (SplitArg.equals (" -device" ))
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+ DeviceSeen = true ;
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+ }
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+ if (DeviceSeen)
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+ break ;
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+ }
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+ if (DeviceArg.empty ())
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+ return false ;
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+
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+ // Go through all of the arguments to '-device' and determine if any of these
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+ // are pvc based. We only match literal values and will not find a match
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+ // when ranges or wildcards are used.
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+ // Here we parse the targets, tokenizing via ','
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+ SmallVector<StringRef> SplitArgs;
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+ DeviceArg.split (SplitArgs, " ," );
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+ for (const auto &SingleArg : SplitArgs) {
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+ StringRef OclocTarget;
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+ // Handle shortened versions.
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+ bool CheckShortVersion = true ;
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+ for (auto Char : SingleArg.str ()) {
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+ if (!std::isdigit (Char) && Char != ' .' ) {
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+ CheckShortVersion = false ;
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+ break ;
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+ }
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+ }
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+ // Check for device, version or hex (literal values)
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+ for (unsigned int I = 0 ; I < std::size (PVCDevices); I++) {
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+ if (SingleArg.equals_insensitive (PVCDevices[I].DeviceName ) ||
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+ SingleArg.equals_insensitive (PVCDevices[I].Version ))
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+ return true ;
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+ for (int HexVal : PVCDevices[I].HexValues ) {
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+ int Value = 0 ;
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+ if (!SingleArg.getAsInteger (0 , Value) && Value == HexVal)
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+ return true ;
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+ }
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+ if (CheckShortVersion &&
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+ StringRef (PVCDevices[I].Version ).starts_with (SingleArg))
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+ return true ;
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+ }
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+ }
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+ return false ;
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+ }
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+
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static llvm::StringMap<StringRef> GRFModeFlagMap{
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{" auto" , " -ze-intel-enable-auto-large-GRF-mode" },
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{" small" , " -ze-intel-128-GRF-per-thread" },
@@ -902,7 +979,7 @@ void SYCL::gen::BackendCompiler::ConstructJob(Compilation &C,
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static_cast <const toolchains::SYCLToolChain &>(getToolChain ());
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const ToolChain *HostTC = C.getSingleOffloadToolChain <Action::OFK_Host>();
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TC.AddImpliedTargetArgs (getToolChain ().getTriple (), Args, CmdArgs, JA,
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- *HostTC);
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+ *HostTC, Device );
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TC.TranslateBackendTargetArgs (getToolChain ().getTriple (), Args, CmdArgs,
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Device);
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TC.TranslateLinkerTargetArgs (getToolChain ().getTriple (), Args, CmdArgs);
@@ -1358,7 +1435,8 @@ void SYCLToolChain::AddImpliedTargetArgs(const llvm::Triple &Triple,
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const llvm::opt::ArgList &Args,
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llvm::opt::ArgStringList &CmdArgs,
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const JobAction &JA,
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- const ToolChain &HostTC) const {
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+ const ToolChain &HostTC,
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+ StringRef Device) const {
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// Current implied args are for debug information and disabling of
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// optimizations. They are passed along to the respective areas as follows:
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// FPGA: -g -cl-opt-disable
@@ -1371,6 +1449,8 @@ void SYCLToolChain::AddImpliedTargetArgs(const llvm::Triple &Triple,
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// string
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llvm::SmallVector<std::pair<StringRef, StringRef>, 16 > PerDeviceArgs;
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bool IsGen = Triple.getSubArch () == llvm::Triple::SPIRSubArch_gen;
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+ bool IsJIT =
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+ Triple.isSPIROrSPIRV () && Triple.getSubArch () == llvm::Triple::NoSubArch;
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if (Arg *A = Args.getLastArg (options::OPT_g_Group, options::OPT__SLASH_Z7))
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if (!A->getOption ().matches (options::OPT_g0))
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BeArgs.push_back (" -g" );
@@ -1401,8 +1481,7 @@ void SYCLToolChain::AddImpliedTargetArgs(const llvm::Triple &Triple,
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// option to honor the user's specification.
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PerDeviceArgs.push_back (
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{DeviceName, Args.MakeArgString (BackendOptName)});
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- } else if (Triple.isSPIROrSPIRV () &&
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- Triple.getSubArch () == llvm::Triple::NoSubArch) {
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+ } else if (IsJIT) {
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// For JIT, pass -ftarget-register-alloc-mode=Device:BackendOpt to
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// clang-offload-wrapper to be processed by the runtime.
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BeArgs.push_back (Args.MakeArgString (RegAllocModeOptName + DeviceName +
@@ -1415,15 +1494,21 @@ void SYCLToolChain::AddImpliedTargetArgs(const llvm::Triple &Triple,
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ProcessElement (Elem);
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} else if (!HostTC.getTriple ().isWindowsMSVCEnvironment ()) {
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// If -ftarget-register-alloc-mode is not specified, the default is
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- // pvc:default on Windows and and pvc:auto otherwise.
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- StringRef DeviceName = " pvc" ;
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- StringRef BackendOptName = SYCL::gen::getGenGRFFlag (" auto" );
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- if (IsGen)
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- PerDeviceArgs.push_back ({DeviceName, Args.MakeArgString (BackendOptName)});
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- else if (Triple.isSPIROrSPIRV () &&
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- Triple.getSubArch () == llvm::Triple::NoSubArch) {
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- BeArgs.push_back (Args.MakeArgString (RegAllocModeOptName + DeviceName +
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- " :" + BackendOptName));
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+ // pvc:default on Windows and and pvc:auto otherwise when -device pvc is
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+ // provided by the user.
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+ ArgStringList TargArgs;
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+ Args.AddAllArgValues (TargArgs, options::OPT_Xs, options::OPT_Xs_separate);
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+ Args.AddAllArgValues (TargArgs, options::OPT_Xsycl_backend);
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+ // Check for any -device settings.
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+ if (IsJIT || Device == " pvc" || hasPVCDevice (TargArgs)) {
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+ StringRef DeviceName = " pvc" ;
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+ StringRef BackendOptName = SYCL::gen::getGenGRFFlag (" auto" );
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+ if (IsGen)
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+ PerDeviceArgs.push_back (
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+ {DeviceName, Args.MakeArgString (BackendOptName)});
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+ else if (IsJIT)
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+ BeArgs.push_back (Args.MakeArgString (RegAllocModeOptName + DeviceName +
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+ " :" + BackendOptName));
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}
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}
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// only pass -vpfp-relaxed for aoc with -fintelfpga and -fp-model=fast
@@ -1468,11 +1553,9 @@ void SYCLToolChain::AddImpliedTargetArgs(const llvm::Triple &Triple,
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if (Args.hasFlag (options::OPT_ftarget_export_symbols,
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options::OPT_fno_target_export_symbols, false ))
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BeArgs.push_back (" -library-compilation" );
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- } else if (Triple.getSubArch () == llvm::Triple::NoSubArch &&
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- Triple.isSPIROrSPIRV ()) {
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+ } else if (IsJIT)
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// -ftarget-compile-fast JIT
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Args.AddLastArg (BeArgs, options::OPT_ftarget_compile_fast);
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- }
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if (IsGen) {
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for (auto [DeviceName, BackendArgStr] : PerDeviceArgs) {
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CmdArgs.push_back (" -device_options" );
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