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[SYCL][CUDA][libclc] implemented atomic min, max and sub
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5 files changed

+143
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‎libclc/ptx-nvidiacl/libspirv/SOURCES

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,7 @@ atomic/atomic_dec.cl
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atomic/atomic_inc.cl
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atomic/atomic_max.cl
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atomic/atomic_min.cl
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atomic/atomic_sub.cl
9798
atomic/atomic_xchg.cl
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atomic/atomic_or.cl
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atomic/atomic_xor.cl

‎libclc/ptx-nvidiacl/libspirv/atomic/atomic_inc_dec_helpers.h

Lines changed: 1 addition & 1 deletion
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@@ -23,7 +23,7 @@
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volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
2424
enum MemorySemanticsMask semantics) { \
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return _Z21__spirv_AtomicIAddEXTPU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
26-
pointer, scope, semantics, 1); \
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pointer, scope, semantics, VAL); \
2727
}
2828

2929
#define __CLC_NVVM_ATOMIC_INCDEC(TYPE, TYPE_MANGLED, OP_MANGLED, VAL) \

‎libclc/ptx-nvidiacl/libspirv/atomic/atomic_max.cl

Lines changed: 51 additions & 0 deletions
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@@ -20,3 +20,54 @@ __CLC_NVVM_ATOMIC(unsigned long, m, unsigned long, ul, max,
2020
#undef __CLC_NVVM_ATOMIC_TYPES
2121
#undef __CLC_NVVM_ATOMIC
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#undef __CLC_NVVM_ATOMIC_IMPL
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24+
#define __CLC_NVVM_ATOMIC_MAX_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, \
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ADDR_SPACE, ADDR_SPACE_MANGLED) \
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TYPE_INT _Z18__spirv_AtomicLoadPU3##ADDR_SPACE_MANGLED##K##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
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volatile ADDR_SPACE const TYPE_INT *, enum Scope, \
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enum MemorySemanticsMask); \
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TYPE_INT \
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_Z29__spirv_AtomicCompareExchange##PU3##ADDR_SPACE_MANGLED##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_INT_MANGLED##TYPE_INT_MANGLED( \
31+
volatile ADDR_SPACE TYPE_INT *, enum Scope, enum MemorySemanticsMask, enum MemorySemanticsMask, \
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TYPE_INT, TYPE_INT); \
33+
_CLC_DECL TYPE \
34+
_Z21__spirv_Atomic##OP_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
35+
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
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enum MemorySemanticsMask semantics, TYPE val) { \
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enum MemorySemanticsMask load_order; \
38+
switch (semantics) { \
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case SequentiallyConsistent: \
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load_order = SequentiallyConsistent; \
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break; \
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case Acquire: \
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case AcquireRelease: \
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load_order = Acquire; \
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break; \
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default: \
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load_order = None; \
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} \
49+
volatile ADDR_SPACE TYPE_INT* pointer_int = (volatile ADDR_SPACE TYPE_INT *)pointer; \
50+
TYPE_INT val_int = *(TYPE_INT*)&val; \
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TYPE_INT old_int = _Z18__spirv_AtomicLoadPU3##ADDR_SPACE_MANGLED##K##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
52+
pointer_int, scope, load_order); \
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TYPE old = *(TYPE*)&old_int; \
54+
while (val > old) { \
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TYPE_INT tmp_int = _Z29__spirv_AtomicCompareExchange##PU3##ADDR_SPACE_MANGLED##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_INT_MANGLED##TYPE_INT_MANGLED( \
56+
pointer_int, scope, semantics, semantics, val_int, old_int); \
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if(old_int == tmp_int){ \
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return *(TYPE*)&tmp_int; \
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} \
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old_int = tmp_int; \
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old = *(TYPE*)&old_int; \
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} \
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return old; \
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}
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66+
#define __CLC_NVVM_ATOMIC_MAX(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED) \
67+
__CLC_NVVM_ATOMIC_MAX_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, __global, \
68+
AS1) \
69+
__CLC_NVVM_ATOMIC_MAX_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, __local, \
70+
AS3)
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72+
__CLC_NVVM_ATOMIC_MAX(float, f, int, i, FMaxEXT)
73+
__CLC_NVVM_ATOMIC_MAX(double, d, long, l, FMaxEXT)

‎libclc/ptx-nvidiacl/libspirv/atomic/atomic_min.cl

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,3 +18,54 @@ __CLC_NVVM_ATOMIC(ulong, m, ulong, ul, min, _Z18__spirv_AtomicUMin)
1818
#undef __CLC_NVVM_ATOMIC_TYPES
1919
#undef __CLC_NVVM_ATOMIC
2020
#undef __CLC_NVVM_ATOMIC_IMPL
21+
22+
#define __CLC_NVVM_ATOMIC_MIN_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, \
23+
ADDR_SPACE, ADDR_SPACE_MANGLED) \
24+
TYPE_INT _Z18__spirv_AtomicLoadPU3##ADDR_SPACE_MANGLED##K##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
25+
volatile ADDR_SPACE const TYPE_INT *, enum Scope, \
26+
enum MemorySemanticsMask); \
27+
TYPE_INT \
28+
_Z29__spirv_AtomicCompareExchange##PU3##ADDR_SPACE_MANGLED##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_INT_MANGLED##TYPE_INT_MANGLED( \
29+
volatile ADDR_SPACE TYPE_INT *, enum Scope, enum MemorySemanticsMask, enum MemorySemanticsMask, \
30+
TYPE_INT, TYPE_INT); \
31+
_CLC_DECL TYPE \
32+
_Z21__spirv_Atomic##OP_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
33+
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
34+
enum MemorySemanticsMask semantics, TYPE val) { \
35+
enum MemorySemanticsMask load_order; \
36+
switch (semantics) { \
37+
case SequentiallyConsistent: \
38+
load_order = SequentiallyConsistent; \
39+
break; \
40+
case Acquire: \
41+
case AcquireRelease: \
42+
load_order = Acquire; \
43+
break; \
44+
default: \
45+
load_order = None; \
46+
} \
47+
volatile ADDR_SPACE TYPE_INT* pointer_int = (volatile ADDR_SPACE TYPE_INT *)pointer; \
48+
TYPE_INT val_int = *(TYPE_INT*)&val; \
49+
TYPE_INT old_int = _Z18__spirv_AtomicLoadPU3##ADDR_SPACE_MANGLED##K##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
50+
pointer_int, scope, load_order); \
51+
TYPE old = *(TYPE*)&old_int; \
52+
while (val < old) { \
53+
TYPE_INT tmp_int = _Z29__spirv_AtomicCompareExchange##PU3##ADDR_SPACE_MANGLED##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_INT_MANGLED##TYPE_INT_MANGLED( \
54+
pointer_int, scope, semantics, semantics, val_int, old_int); \
55+
if(old_int == tmp_int){ \
56+
return *(TYPE*)&tmp_int; \
57+
} \
58+
old_int = tmp_int; \
59+
old = *(TYPE*)&old_int; \
60+
} \
61+
return old; \
62+
}
63+
64+
#define __CLC_NVVM_ATOMIC_MIN(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED) \
65+
__CLC_NVVM_ATOMIC_MIN_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, __global, \
66+
AS1) \
67+
__CLC_NVVM_ATOMIC_MIN_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, __local, \
68+
AS3)
69+
70+
__CLC_NVVM_ATOMIC_MIN(float, f, int, i, FMinEXT)
71+
__CLC_NVVM_ATOMIC_MIN(double, d, long, l, FMinEXT)

‎libclc/ptx-nvidiacl/libspirv/atomic/atomic_sub.cl

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
//===----------------------------------------------------------------------===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
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//===----------------------------------------------------------------------===//
8+
9+
10+
#include <spirv/spirv.h>
11+
#include <spirv/spirv_types.h>
12+
13+
#define __CLC_NVVM_ATOMIC_SUB_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, \
14+
ADDR_SPACE, ADDR_SPACE_MANGLED) \
15+
TYPE \
16+
_Z18__spirv_AtomicIAddPU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
17+
volatile ADDR_SPACE TYPE *, enum Scope, enum MemorySemanticsMask, \
18+
TYPE); \
19+
_CLC_DECL TYPE \
20+
_Z18__spirv_Atomic##OP_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
21+
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
22+
enum MemorySemanticsMask semantics, TYPE val) { \
23+
return _Z18__spirv_AtomicIAddPU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
24+
pointer, scope, semantics, -val); \
25+
}
26+
27+
#define __CLC_NVVM_ATOMIC_SUB(TYPE, TYPE_MANGLED, OP_MANGLED) \
28+
__CLC_NVVM_ATOMIC_SUB_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, __global, \
29+
AS1) \
30+
__CLC_NVVM_ATOMIC_SUB_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, __local, \
31+
AS3)
32+
33+
__CLC_NVVM_ATOMIC_SUB(int, i, ISub)
34+
__CLC_NVVM_ATOMIC_SUB(unsigned int, j, ISub)
35+
__CLC_NVVM_ATOMIC_SUB(long, l, ISub)
36+
__CLC_NVVM_ATOMIC_SUB(unsigned long, m, ISub)
37+
38+
#undef __CLC_NVVM_ATOMIC_SUB_IMPL
39+
#undef __CLC_NVVM_ATOMIC_SUB

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