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1 parent 70ec903 commit 7d1d83dCopy full SHA for 7d1d83d
llvm-spirv/lib/SPIRV/SPIRVWriter.cpp
@@ -5735,8 +5735,8 @@ bool LLVMToSPIRVBase::transExecutionMode() {
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break;
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unsigned NBarrierCnt = 0;
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N.get(NBarrierCnt);
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- BF->addExecutionMode(new SPIRVExecutionMode(
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- BF, static_cast<ExecutionMode>(EMode), NBarrierCnt));
+ BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
+ BF, static_cast<ExecutionMode>(EMode), NBarrierCnt)));
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BM->addExtension(ExtensionID::SPV_INTEL_vector_compute);
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BM->addCapability(CapabilityVectorComputeINTEL);
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} break;
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