Merge branch 'sycl' of https://github.com/intel/llvm into esimd_emu_promot_memory_intrinsic

Author: dongkyunahn-intel

.github/CODEOWNERS

@@ -50,6 +50,6 @@ clang/tools/clang-offload-*/ @intel/dpcpp-tools-reviewers
 # Explicit SIMD
 ESIMD/ @intel/dpcpp-esimd-reviewers
 esimd/ @intel/dpcpp-esimd-reviewers
-sycl/include/sycl/ext/intel/experimental/esimd.hpp @intel/dpcpp-esimd-reviewers
+sycl/include/sycl/ext/intel/esimd.hpp @intel/dpcpp-esimd-reviewers
 sycl/doc/extensions/experimental/sycl_ext_intel_esimd/ @intel/dpcpp-esimd-reviewers
 llvm/lib/SYCLLowerIR/CMakeLists.txt @intel/dpcpp-tools-reviewers @intel/dpcpp-esimd-reviewers

.github/workflows/llvm-bugs.yml

@@ -48,6 +48,7 @@ jobs:
                 to: "[email protected]",
                 subject: `[Bug ${issue.data.number}] ${issue.data.title}`,
                 template: "new-github-issue",
+                'o:tracking-clicks': 'no',
                 'h:X-Mailgun-Variables': JSON.stringify(payload)
               };
 

.github/workflows/sycl_linux_build_and_test.yml

@@ -15,10 +15,6 @@ on:
         type: string
         required: false
         default: "ghcr.io/intel/llvm/ubuntu2004_build:latest"
-      build_runs_on:
-        type: string
-        required: false
-        default: "build"
       build_ref:
         type: string
         required: false
@@ -36,7 +32,7 @@ on:
       build_configure_extra_args:
         type: string
         required: false
-        default: "--hip --cuda"
+        default: "--hip --cuda --enable-esimd-emulator"
       build_artifact_suffix:
         type: string
         required: true
@@ -68,7 +64,7 @@ on:
 jobs:
   build:
     name: Build + LIT
-    runs-on: ${{ inputs.build_runs_on }}
+    runs-on: [Linux, build]
     container:
       image: ${{ inputs.build_image }}
       options: -u 1001:1001
@@ -204,6 +200,11 @@ jobs:
       image: ${{ matrix.image }}
       options: ${{ matrix.container_options }}
     steps:
+    - name: Reset GPU
+      if: ${{ contains(matrix.config, 'gen9') }}
+      run: |
+        sudo mount -t debugfs none /sys/kernel/debug
+        sudo bash -c 'echo 1 > /sys/kernel/debug/dri/0/i915_wedged'
     - run: cp -r /actions .
     - name: Register cleanup after job is finished
       uses: ./actions/cleanup

.github/workflows/sycl_nightly.yml

@@ -64,7 +64,6 @@ jobs:
     if: github.repository == 'intel/llvm'
     uses: ./.github/workflows/sycl_linux_build_and_test.yml
     with:
-      build_runs_on: build
       build_cache_root: "/__w/"
       build_cache_suffix: new_pm
       build_artifact_suffix: new_pm

.github/workflows/sycl_post_commit.yml

@@ -15,14 +15,12 @@ jobs:
     name: Linux Default
     uses: ./.github/workflows/sycl_linux_build_and_test.yml
     with:
-      build_runs_on: build
       build_cache_root: "/__w/llvm"
       build_artifact_suffix: default
   linux_no_assert:
     name: Linux (no assert)
     uses: ./.github/workflows/sycl_linux_build_and_test.yml
     with:
-      build_runs_on: build
       build_cache_root: "/__w/llvm"
       build_cache_suffix: gcc_no_assertions
       build_artifact_suffix: gcc_no_assertions

.github/workflows/sycl_precommit.yml

@@ -35,9 +35,8 @@ jobs:
     if: always() && (success() || contains(github.event.pull_request.labels.*.name, 'ignore-lint'))
     uses: ./.github/workflows/sycl_linux_build_and_test.yml
     with:
-      build_runs_on: "build"
       build_cache_root: "/__w/"
       build_cache_size: "8G"
       build_artifact_suffix: "default"
       build_cache_suffix: "default"
-      lts_config: "hip_amdgpu;ocl_x64;ocl_gen9;l0_gen9"
+      lts_config: "hip_amdgpu;ocl_x64;ocl_gen9;l0_gen9;esimd_emu"

.mailmap

@@ -16,7 +16,7 @@
 # Combinations of both are possible too, see
 # https://git-scm.com/docs/gitmailmap for format details.
 #
-# You can commit changes for your own names and  email addresses without review.
+# You can commit changes for your own names and email addresses without review.
 # If you want to add entries for other people, please have them review the
 # addition.
 #

bolt/include/bolt/Core/BinaryFunction.h

@@ -1299,10 +1299,11 @@ class BinaryFunction {
     case ELF::R_X86_64_32:
     case ELF::R_X86_64_32S:
     case ELF::R_X86_64_64:
+    case ELF::R_X86_64_PC8:
+    case ELF::R_X86_64_PC32:
+    case ELF::R_X86_64_PC64:
       Relocations[Offset] = Relocation{Offset, Symbol, RelType, Addend, Value};
       return;
-    case ELF::R_X86_64_PC32:
-    case ELF::R_X86_64_PC8:
     case ELF::R_X86_64_PLT32:
     case ELF::R_X86_64_GOTPCRELX:
     case ELF::R_X86_64_REX_GOTPCRELX:

bolt/include/bolt/Core/DebugData.h

@@ -490,6 +490,7 @@ class DebugInfoBinaryPatcher : public SimpleBinaryPatcher {
     PatchBaseClass,
     PatchValue32,
     PatchValue64to32,
+    PatchValue32GenericSize,
     PatchValue64,
     PatchValueVariable,
     ReferencePatchValue,
@@ -536,6 +537,22 @@ class DebugInfoBinaryPatcher : public SimpleBinaryPatcher {
     uint32_t Value;
   };
 
+  /// Patch for 4 byte entry, where original entry size is not 4 bytes or 8
+  /// bytes.
+  struct DebugPatch32GenericSize : public Patch {
+    DebugPatch32GenericSize(uint32_t O, uint32_t V, uint32_t OVS)
+        : Patch(O, DebugPatchKind::PatchValue32GenericSize) {
+      Value = V;
+      OldValueSize = OVS;
+    }
+
+    static bool classof(const Patch *Writer) {
+      return Writer->getKind() == DebugPatchKind::PatchValue32GenericSize;
+    }
+    uint32_t Value;
+    uint32_t OldValueSize;
+  };
+
   struct DebugPatch64 : public Patch {
     DebugPatch64(uint32_t O, uint64_t V)
         : Patch(O, DebugPatchKind::PatchValue64) {
@@ -693,6 +710,9 @@ class DebugInfoBinaryPatcher : public SimpleBinaryPatcher {
       case DebugPatchKind::PatchValue64to32:
         delete reinterpret_cast<DebugPatch64to32 *>(P);
         break;
+      case DebugPatchKind::PatchValue32GenericSize:
+        delete reinterpret_cast<DebugPatch32GenericSize *>(P);
+        break;
       case DebugPatchKind::PatchValue64:
         delete reinterpret_cast<DebugPatch64 *>(P);
         break;

bolt/include/bolt/Core/MCPlusBuilder.h

@@ -424,9 +424,7 @@ class MCPlusBuilder {
 
   /// Return a register number that is guaranteed to not match with
   /// any real register on the underlying architecture.
-  virtual MCPhysReg getNoRegister() const {
-    llvm_unreachable("not implemented");
-  }
+  MCPhysReg getNoRegister() const { return MCRegister::NoRegister; }
 
   /// Return a register corresponding to a function integer argument \p ArgNo
   /// if the argument is passed in a register. Or return the result of
@@ -1327,6 +1325,16 @@ class MCPlusBuilder {
     return IndirectBranchType::UNKNOWN;
   }
 
+  /// Analyze branch \p Instruction in PLT section and try to determine
+  /// associated got entry address.
+  virtual uint64_t analyzePLTEntry(MCInst &Instruction,
+                                   InstructionIterator Begin,
+                                   InstructionIterator End,
+                                   uint64_t BeginPC) const {
+    llvm_unreachable("not implemented");
+    return 0;
+  }
+
   virtual bool analyzeVirtualMethodCall(InstructionIterator Begin,
                                         InstructionIterator End,
                                         std::vector<MCInst *> &MethodFetchInsns,

bolt/include/bolt/Core/Relocation.h

@@ -49,7 +49,7 @@ struct Relocation {
   /// Used to validate relocation correctness.
   uint64_t Value;
 
-  /// Return size of the given relocation \p Type.
+  /// Return size in bytes of the given relocation \p Type.
   static size_t getSizeForType(uint64_t Type);
 
   /// Return size of this relocation.

bolt/include/bolt/Rewrite/RewriteInstance.h

@@ -56,7 +56,7 @@ class RewriteInstance {
   Error setProfile(StringRef Filename);
 
   /// Run all the necessary steps to read, optimize and rewrite the binary.
-  void run();
+  Error run();
 
   /// Diff this instance against another one. Non-const since we may run passes
   /// to fold identical functions.
@@ -218,7 +218,7 @@ class RewriteInstance {
 
   /// Detect addresses and offsets available in the binary for allocating
   /// new sections.
-  void discoverStorage();
+  Error discoverStorage();
 
   /// Adjust function sizes and set proper maximum size values after the whole
   /// symbol table has been processed.
@@ -246,6 +246,19 @@ class RewriteInstance {
   /// Disassemble and create function entries for PLT.
   void disassemblePLT();
 
+  /// Auxiliary function to create .plt BinaryFunction on \p EntryAddres
+  /// with the \p EntrySize size. \p TargetAddress is the .got entry
+  /// associated address.
+  void createPLTBinaryFunction(uint64_t TargetAddress, uint64_t EntryAddress,
+                               uint64_t EntrySize);
+
+  /// Disassemble aarch64-specific .plt \p Section auxiliary function
+  void disassemblePLTSectionAArch64(BinarySection &Section);
+
+  /// Disassemble X86-specific .plt \p Section auxiliary function. \p EntrySize
+  /// is the expected .plt \p Section entry function size.
+  void disassemblePLTSectionX86(BinarySection &Section, uint64_t EntrySize);
+
   /// ELF-specific part. TODO: refactor into new class.
 #define ELF_FUNCTION(FUNC)                                                     \
   template <typename ELFT> void FUNC(object::ELFObjectFile<ELFT> *Obj);        \
@@ -473,7 +486,7 @@ class RewriteInstance {
   /// multiple variants generated by different linkers.
   struct PLTSectionInfo {
     const char *Name;
-    uint64_t EntrySize;
+    uint64_t EntrySize{0};
   };
 
   /// Different types of X86-64 PLT sections.
@@ -485,10 +498,7 @@ class RewriteInstance {
   };
 
   /// AArch64 PLT sections.
-  const PLTSectionInfo AArch64_PLTSections[2] = {
-      { ".plt", 16 },
-      { nullptr, 0 }
-  };
+  const PLTSectionInfo AArch64_PLTSections[2] = {{".plt"}, {nullptr}};
 
   /// Return PLT information for a section with \p SectionName or nullptr
   /// if the section is not PLT.

bolt/lib/Core/BinaryFunction.cpp

@@ -1265,51 +1265,6 @@ bool BinaryFunction::disassemble() {
       }
     }
 
-    // Check if there's a relocation associated with this instruction.
-    bool UsedReloc = false;
-    for (auto Itr = Relocations.lower_bound(Offset),
-              ItrE = Relocations.lower_bound(Offset + Size);
-         Itr != ItrE; ++Itr) {
-      const Relocation &Relocation = Itr->second;
-
-      LLVM_DEBUG(dbgs() << "BOLT-DEBUG: replacing immediate 0x"
-                        << Twine::utohexstr(Relocation.Value)
-                        << " with relocation"
-                           " against "
-                        << Relocation.Symbol << "+" << Relocation.Addend
-                        << " in function " << *this
-                        << " for instruction at offset 0x"
-                        << Twine::utohexstr(Offset) << '\n');
-
-      // Process reference to the primary symbol.
-      if (!Relocation.isPCRelative())
-        BC.handleAddressRef(Relocation.Value - Relocation.Addend, *this,
-                            /*IsPCRel*/ false);
-
-      int64_t Value = Relocation.Value;
-      const bool Result = BC.MIB->replaceImmWithSymbolRef(
-          Instruction, Relocation.Symbol, Relocation.Addend, Ctx.get(), Value,
-          Relocation.Type);
-      (void)Result;
-      assert(Result && "cannot replace immediate with relocation");
-
-      // For aarch, if we replaced an immediate with a symbol from a
-      // relocation, we mark it so we do not try to further process a
-      // pc-relative operand. All we need is the symbol.
-      if (BC.isAArch64())
-        UsedReloc = true;
-
-      // Make sure we replaced the correct immediate (instruction
-      // can have multiple immediate operands).
-      if (BC.isX86()) {
-        assert(truncateToSize(static_cast<uint64_t>(Value),
-                              Relocation::getSizeForType(Relocation.Type)) ==
-                   truncateToSize(Relocation.Value, Relocation::getSizeForType(
-                                                        Relocation.Type)) &&
-               "immediate value mismatch in function");
-      }
-    }
-
     if (MIB->isBranch(Instruction) || MIB->isCall(Instruction)) {
       uint64_t TargetAddress = 0;
       if (MIB->evaluateBranch(Instruction, AbsoluteInstrAddr, Size,
@@ -1394,8 +1349,75 @@ bool BinaryFunction::disassemble() {
         if (BC.isAArch64())
           handleAArch64IndirectCall(Instruction, Offset);
       }
-    } else if (MIB->hasPCRelOperand(Instruction) && !UsedReloc) {
-      handlePCRelOperand(Instruction, AbsoluteInstrAddr, Size);
+    } else {
+      // Check if there's a relocation associated with this instruction.
+      bool UsedReloc = false;
+      for (auto Itr = Relocations.lower_bound(Offset),
+                ItrE = Relocations.lower_bound(Offset + Size);
+           Itr != ItrE; ++Itr) {
+        const Relocation &Relocation = Itr->second;
+        uint64_t SymbolValue = Relocation.Value - Relocation.Addend;
+        if (Relocation.isPCRelative())
+          SymbolValue += getAddress() + Relocation.Offset;
+
+        // Process reference to the symbol.
+        if (BC.isX86())
+          BC.handleAddressRef(SymbolValue, *this, Relocation.isPCRelative());
+
+        if (BC.isAArch64() || !Relocation.isPCRelative()) {
+          int64_t Value = Relocation.Value;
+          const bool Result = BC.MIB->replaceImmWithSymbolRef(
+              Instruction, Relocation.Symbol, Relocation.Addend, Ctx.get(),
+              Value, Relocation.Type);
+          (void)Result;
+          assert(Result && "cannot replace immediate with relocation");
+
+          if (BC.isX86()) {
+            // Make sure we replaced the correct immediate (instruction
+            // can have multiple immediate operands).
+            assert(
+                truncateToSize(static_cast<uint64_t>(Value),
+                               Relocation::getSizeForType(Relocation.Type)) ==
+                    truncateToSize(Relocation.Value, Relocation::getSizeForType(
+                                                         Relocation.Type)) &&
+                "immediate value mismatch in function");
+          } else if (BC.isAArch64()) {
+            // For aarch, if we replaced an immediate with a symbol from a
+            // relocation, we mark it so we do not try to further process a
+            // pc-relative operand. All we need is the symbol.
+            UsedReloc = true;
+          }
+        } else {
+          // Check if the relocation matches memop's Disp.
+          uint64_t TargetAddress;
+          if (!BC.MIB->evaluateMemOperandTarget(Instruction, TargetAddress,
+                                                AbsoluteInstrAddr, Size)) {
+            errs() << "BOLT-ERROR: PC-relative operand can't be evaluated\n";
+            exit(1);
+          }
+          assert(TargetAddress == Relocation.Value + AbsoluteInstrAddr + Size &&
+                 "Immediate value mismatch detected.");
+
+          const MCExpr *Expr = MCSymbolRefExpr::create(
+              Relocation.Symbol, MCSymbolRefExpr::VK_None, *BC.Ctx);
+          // Real addend for pc-relative targets is adjusted with a delta
+          // from relocation placement to the next instruction.
+          const uint64_t TargetAddend =
+              Relocation.Addend + Offset + Size - Relocation.Offset;
+          if (TargetAddend) {
+            const MCConstantExpr *Offset =
+                MCConstantExpr::create(TargetAddend, *BC.Ctx);
+            Expr = MCBinaryExpr::createAdd(Expr, Offset, *BC.Ctx);
+          }
+          BC.MIB->replaceMemOperandDisp(
+              Instruction, MCOperand::createExpr(BC.MIB->getTargetExprFor(
+                               Instruction, Expr, *BC.Ctx, 0)));
+          UsedReloc = true;
+        }
+      }
+
+      if (MIB->hasPCRelOperand(Instruction) && !UsedReloc)
+        handlePCRelOperand(Instruction, AbsoluteInstrAddr, Size);
     }
 
 add_instruction:
@@ -1565,6 +1587,8 @@ bool BinaryFunction::scanExternalRefs() {
               ItrE = Relocations.lower_bound(Offset + Size);
          Itr != ItrE; ++Itr) {
       Relocation &Relocation = Itr->second;
+      if (Relocation.isPCRelative() && BC.isX86())
+        continue;
       if (ignoreReference(Relocation.Symbol))
         continue;