Merge branch 'intel:sycl' into sycl

Author: zjin-lcf

.gitignore

@@ -13,6 +13,8 @@
 *~
 # Merge files created by git.
 *.orig
+# Reject files created by patch.
+*.rej
 # Byte compiled python modules.
 *.pyc
 # vim swap files

bolt/CMakeLists.txt

@@ -5,7 +5,7 @@ set(BOLT_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR})
 set(CMAKE_CXX_STANDARD 14)
 
 set(BOLT_ENABLE_RUNTIME OFF)
-if (CMAKE_HOST_SYSTEM_PROCESSOR MATCHES "x86_64")
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
   set(BOLT_ENABLE_RUNTIME ON)
 endif()
 
@@ -16,26 +16,31 @@ architecture for use in BOLT tests")
 
 set(BOLT_INCLUDE_TESTS OFF)
 if (LLVM_INCLUDE_TESTS)
+  set(BOLT_CLANG_PRESENT OFF)
+  set(BOLT_LLD_PRESENT OFF)
+
+  if ("clang" IN_LIST LLVM_ENABLE_PROJECTS AND BOLT_CLANG_EXE)
+    message(WARNING "BOLT_CLANG_EXE is set and clang project is enabled. \
+          BOLT_CLANG_EXE will be used for BOLT tests.")
+  endif()
   if ("clang" IN_LIST LLVM_ENABLE_PROJECTS OR BOLT_CLANG_EXE)
-    if ("clang" IN_LIST LLVM_ENABLE_PROJECTS AND BOLT_CLANG_EXE)
-      message(WARNING "BOLT_CLANG_EXE is set and clang project is enabled. \
-            BOLT_CLANG_EXE will be used for BOLT tests.")
-    endif()
-    if ("lld" IN_LIST LLVM_ENABLE_PROJECTS OR BOLT_LLD_EXE)
-      if ("lld" IN_LIST LLVM_ENABLE_PROJECTS AND BOLT_LLD_EXE)
-        message(WARNING "BOLT_LLD_EXE is set and lld project is enabled. \
-              BOLT_LLD_EXE will be used for BOLT tests.")
-      endif()
-      set(BOLT_INCLUDE_TESTS ON)
-    else()
-      message(WARNING "Not including BOLT tests since lld is disabled. \
-            Enable lld in LLVM_ENABLE_PROJECTS or provide a path to lld binary \
-            in BOLT_LLD_EXE.")
-    endif()
+    set(BOLT_CLANG_PRESENT ON)
+  endif()
+
+  if ("lld" IN_LIST LLVM_ENABLE_PROJECTS AND BOLT_LLD_EXE)
+    message(WARNING "BOLT_LLD_EXE is set and lld project is enabled. \
+          BOLT_LLD_EXE will be used for BOLT tests.")
+  endif()
+  if ("lld" IN_LIST LLVM_ENABLE_PROJECTS OR BOLT_LLD_EXE)
+    set(BOLT_LLD_PRESENT ON)
+  endif()
+
+  if (BOLT_CLANG_PRESENT AND BOLT_LLD_PRESENT)
+    set(BOLT_INCLUDE_TESTS ON)
   else()
-    message(WARNING "Not including BOLT tests since clang is disabled. \
-          Enable clang in LLVM_ENABLE_PROJECTS or provide a path to clang \
-          binary in BOLT_CLANG_EXE.")
+    message(WARNING "Not including BOLT tests since clang or lld is disabled. \
+          Add clang and lld to LLVM_ENABLE_PROJECTS or provide paths to clang \
+          and lld binaries in BOLT_CLANG_EXE and BOLT_LLD_EXE.")
   endif()
 endif()
 

bolt/include/bolt/Core/BinaryContext.h

@@ -204,6 +204,9 @@ class BinaryContext {
   using DWOIdToCUMapType = std::unordered_map<uint64_t, DWARFUnit *>;
   DWOIdToCUMapType DWOCUs;
 
+  bool ContainsDwarf5{false};
+  bool ContainsDwarfLegacy{false};
+
   /// Preprocess DWO debug information.
   void preprocessDWODebugInfo();
 
@@ -234,7 +237,13 @@ class BinaryContext {
   /// Get Number of DWOCUs in a map.
   uint32_t getNumDWOCUs() { return DWOCUs.size(); }
 
-  const std::map<unsigned, DwarfLineTable> &getDwarfLineTables() const {
+  /// Returns true if DWARF5 is used.
+  bool isDWARF5Used() const { return ContainsDwarf5; }
+
+  /// Returns true if DWARF4 or lower is used.
+  bool isDWARFLegacyUsed() const { return ContainsDwarfLegacy; }
+
+  std::map<unsigned, DwarfLineTable> &getDwarfLineTables() {
     return DwarfLineTablesCUMap;
   }
 
@@ -245,7 +254,8 @@ class BinaryContext {
   Expected<unsigned> getDwarfFile(StringRef Directory, StringRef FileName,
                                   unsigned FileNumber,
                                   Optional<MD5::MD5Result> Checksum,
-                                  Optional<StringRef> Source, unsigned CUID);
+                                  Optional<StringRef> Source, unsigned CUID,
+                                  unsigned DWARFVersion);
 
   /// [start memory address] -> [segment info] mapping.
   std::map<uint64_t, SegmentInfo> SegmentMapInfo;

bolt/include/bolt/Core/BinaryFunction.h

@@ -1279,6 +1279,9 @@ class BinaryFunction {
     case ELF::R_AARCH64_MOVW_UABS_G2:
     case ELF::R_AARCH64_MOVW_UABS_G2_NC:
     case ELF::R_AARCH64_MOVW_UABS_G3:
+    case ELF::R_AARCH64_PREL16:
+    case ELF::R_AARCH64_PREL32:
+    case ELF::R_AARCH64_PREL64:
       Rels[Offset] = Relocation{Offset, Symbol, RelType, Addend, Value};
       return;
     case ELF::R_AARCH64_CALL26: