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[SYCL] Add clang support for FPGA kernel attribute scheduler_target_fmax_mhz
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clang/include/clang/Basic/Attr.td

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@@ -1225,6 +1225,15 @@ def SYCLIntelNumSimdWorkItems : InheritableAttr {
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let PragmaAttributeSupport = 0;
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}
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def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
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let Spellings = [CXX11<"intelfpga","scheduler_target_fmax_mhz">];
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let Args = [UnsignedArgument<"Number">];
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let LangOpts = [SYCLIsDevice, SYCLIsHost];
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let Subjects = SubjectList<[Function], ErrorDiag>;
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let Documentation = [SYCLIntelSchedulerTargetFmaxMhzAttrDocs];
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let PragmaAttributeSupport = 0;
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}
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def SYCLIntelMaxWorkGroupSize : InheritableAttr {
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let Spellings = [CXX11<"intelfpga","max_work_group_size">];
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let Args = [UnsignedArgument<"XDim">,

clang/include/clang/Basic/AttrDocs.td

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@@ -2197,6 +2197,17 @@ device kernel, the attribute is ignored and it is not propagated to a kernel.
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}];
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}
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def SYCLIntelSchedulerTargetFmaxMhzAttrDocs : Documentation {
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let Category = DocCatFunction;
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let Heading = "scheduler_target_fmax_mhz (IntelFPGA)";
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let Content = [{
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Applies to a device function/lambda function. Indicates that the kernel should
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be pipelined so as to achieve the specified target clock frequency (Fmax) of N
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MHz. The argument N may be a template parameter. This attribute should be
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ignored for the FPGA emulator device.
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}];
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}
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def SYCLIntelNoGlobalWorkOffsetAttrDocs : Documentation {
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let Category = DocCatFunction;
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let Heading = "no_global_work_offset (IntelFPGA)";

clang/lib/CodeGen/CodeGenFunction.cpp

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@@ -639,6 +639,14 @@ void CodeGenFunction::EmitOpenCLKernelMetadata(const FunctionDecl *FD,
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llvm::MDNode::get(Context, AttrMDArgs));
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}
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if (const SYCLIntelSchedulerTargetFmaxMhzAttr *A =
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FD->getAttr<SYCLIntelSchedulerTargetFmaxMhzAttr>()) {
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llvm::Metadata *AttrMDArgs[] = {
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llvm::ConstantAsMetadata::get(Builder.getInt32(A->getNumber()))};
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Fn->setMetadata("scheduler_target_fmax_mhz",
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llvm::MDNode::get(Context, AttrMDArgs));
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}
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if (const SYCLIntelMaxWorkGroupSizeAttr *A =
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FD->getAttr<SYCLIntelMaxWorkGroupSizeAttr>()) {
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llvm::Metadata *AttrMDArgs[] = {

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