Handle OpSpecConstantOp with VectorShuffle

Modify the `SPIRVShuffleVector` constructor to allow passing a nullptr
basic block (as is the case for variable initializers).

Modify the `SPIRVShuffleVector` constructor to take `SPIRVId`s instead
of `SPIRVValue`s, which better reflects what is stored in the class,
and saves us an unnecessary ID-to-Value-to-ID round trip in
`createInstFromSpecConstantOp`.

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@72f99e3

Author: svenvh

llvm-spirv/lib/SPIRV/SPIRVReader.cpp

@@ -2375,11 +2375,14 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F,
       else
         Components.push_back(ConstantInt::get(Int32Ty, I));
     }
-    return mapValue(BV,
-                    new ShuffleVectorInst(transValue(VS->getVector1(), F, BB),
-                                          transValue(VS->getVector2(), F, BB),
-                                          ConstantVector::get(Components),
-                                          BV->getName(), BB));
+    IRBuilder<> Builder(*Context);
+    if (BB) {
+      Builder.SetInsertPoint(BB);
+    }
+    return mapValue(BV, Builder.CreateShuffleVector(
+                            transValue(VS->getVector1(), F, BB),
+                            transValue(VS->getVector2(), F, BB),
+                            ConstantVector::get(Components), BV->getName()));
   }
 
   case OpBitReverse: {

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.cpp

@@ -245,6 +245,14 @@ SPIRVInstruction *createInstFromSpecConstantOp(SPIRVSpecConstantOp *Inst) {
          "Op code not allowed for OpSpecConstantOp");
   Ops.erase(Ops.begin(), Ops.begin() + 1);
   switch (OC) {
+  case OpVectorShuffle: {
+    std::vector<SPIRVWord> Comp;
+    for (auto I = Ops.begin() + 2, E = Ops.end(); I != E; ++I) {
+      Comp.push_back(*I);
+    }
+    return new SPIRVVectorShuffle(Inst->getId(), Inst->getType(), Ops[0],
+                                  Ops[1], Comp, nullptr, Inst->getModule());
+  }
   case OpSelect:
     return new SPIRVSelect(Inst->getId(), Inst->getType(), Ops[0], Ops[1],
                            Ops[2], nullptr, Inst->getModule());

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h

@@ -2179,16 +2179,14 @@ class SPIRVVectorShuffle : public SPIRVInstruction {
   const static Op OC = OpVectorShuffle;
   const static SPIRVWord FixedWordCount = 5;
   // Complete constructor
-  SPIRVVectorShuffle(SPIRVId TheId, SPIRVType *TheType, SPIRVValue *TheVector1,
-                     SPIRVValue *TheVector2,
+  SPIRVVectorShuffle(SPIRVId TheId, SPIRVType *TheType, SPIRVId TheVector1,
+                     SPIRVId TheVector2,
                      const std::vector<SPIRVWord> &TheComponents,
-                     SPIRVBasicBlock *TheBB)
+                     SPIRVBasicBlock *TheBB, SPIRVModule *TheM)
       : SPIRVInstruction(TheComponents.size() + FixedWordCount, OC, TheType,
-                         TheId, TheBB),
-        Vector1(TheVector1->getId()), Vector2(TheVector2->getId()),
-        Components(TheComponents) {
+                         TheId, TheBB, TheM),
+        Vector1(TheVector1), Vector2(TheVector2), Components(TheComponents) {
     validate();
-    assert(TheBB && "Invalid BB");
   }
   // Incomplete constructor
   SPIRVVectorShuffle()

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp

@@ -1367,8 +1367,10 @@ SPIRVInstruction *SPIRVModuleImpl::addVectorInsertDynamicInst(
 SPIRVValue *SPIRVModuleImpl::addVectorShuffleInst(
     SPIRVType *Type, SPIRVValue *Vec1, SPIRVValue *Vec2,
     const std::vector<SPIRVWord> &Components, SPIRVBasicBlock *BB) {
-  return addInstruction(
-      new SPIRVVectorShuffle(getId(), Type, Vec1, Vec2, Components, BB), BB);
+  return addInstruction(new SPIRVVectorShuffle(getId(), Type, Vec1->getId(),
+                                               Vec2->getId(), Components, BB,
+                                               this),
+                        BB);
 }
 
 SPIRVInstruction *SPIRVModuleImpl::addBranchInst(SPIRVLabel *TargetLabel,

llvm-spirv/test/SpecConstants/specconstantop-init.spvasm

@@ -30,6 +30,7 @@
 ; CHECK: @var_bitor = addrspace(1) global i32 -3
 ; CHECK: @var_bitxor = addrspace(1) global i32 -55
 ; CHECK: @var_bitand = addrspace(1) global i32 52
+; CHECK: @var_vecshuf = addrspace(1) global <2 x i32> <i32 4, i32 53>
 ; CHECK: @var_logor = addrspace(1) global i1 true
 ; CHECK: @var_logand = addrspace(1) global i1 false
 ; CHECK: @var_lognot = addrspace(1) global i1 false
@@ -76,6 +77,7 @@
                OpDecorate %var_bitor LinkageAttributes "var_bitor" Export
                OpDecorate %var_bitxor LinkageAttributes "var_bitxor" Export
                OpDecorate %var_bitand LinkageAttributes "var_bitand" Export
+               OpDecorate %var_vecshuf LinkageAttributes "var_vecshuf" Export
                OpDecorate %var_logor LinkageAttributes "var_logor" Export
                OpDecorate %var_logand LinkageAttributes "var_logand" Export
                OpDecorate %var_lognot LinkageAttributes "var_lognot" Export
@@ -99,11 +101,14 @@
       %uchar = OpTypeInt 8 0
        %uint = OpTypeInt 32 0
       %float = OpTypeFloat 32
+      %v2i32 = OpTypeVector %uint 2
      %uint_0 = OpConstant %uint 0
      %uint_4 = OpConstant %uint 4
     %uint_53 = OpConstant %uint 53
   %uint_min4 = OpConstant %uint 0xfffffffc
     %float_1 = OpConstant %float 1.0
+   %vec_53_0 = OpConstantComposite %v2i32 %uint_53 %uint_0
+    %vec_4_4 = OpConstantComposite %v2i32 %uint_4 %uint_4
    %sconvert = OpSpecConstantOp %uchar SConvert %uint_53
    %uconvert = OpSpecConstantOp %uchar UConvert %uint_53
     %snegate = OpSpecConstantOp %uint SNegate %uint_53
@@ -125,6 +130,7 @@
       %bitor = OpSpecConstantOp %uint BitwiseOr %uint_53 %uint_min4
      %bitxor = OpSpecConstantOp %uint BitwiseXor %uint_53 %uint_min4
      %bitand = OpSpecConstantOp %uint BitwiseAnd %uint_53 %uint_min4
+    %vecshuf = OpSpecConstantOp %v2i32 VectorShuffle %vec_53_0 %vec_4_4 2 0
       %logor = OpSpecConstantOp %bool LogicalOr %true %false
      %logand = OpSpecConstantOp %bool LogicalAnd %true %false
      %lognot = OpSpecConstantOp %bool LogicalNot %true
@@ -145,6 +151,7 @@
  %_ptr_uchar = OpTypePointer CrossWorkgroup %uchar
   %_ptr_uint = OpTypePointer CrossWorkgroup %uint
   %_ptr_bool = OpTypePointer CrossWorkgroup %bool
+ %_ptr_v2i32 = OpTypePointer CrossWorkgroup %v2i32
        %void = OpTypeVoid
          %14 = OpTypeFunction %void
 
@@ -169,6 +176,7 @@
   %var_bitor = OpVariable %_ptr_uint CrossWorkgroup %bitor
  %var_bitxor = OpVariable %_ptr_uint CrossWorkgroup %bitxor
  %var_bitand = OpVariable %_ptr_uint CrossWorkgroup %bitand
+%var_vecshuf = OpVariable %_ptr_v2i32 CrossWorkgroup %vecshuf
   %var_logor = OpVariable %_ptr_bool CrossWorkgroup %logor
  %var_logand = OpVariable %_ptr_bool CrossWorkgroup %logand
  %var_lognot = OpVariable %_ptr_bool CrossWorkgroup %lognot