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RKSimonRKSimon
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[SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and generic ISD::SRL handling.
As mentioned by @nikic on rGef5debac4302 (although that was just about SHL), we can merge the guaranteed top zero bits from the shifted value, and then, if a min shift amount is known, zero out the top bits as well. SHL tests / handling will be added in a follow up patch.
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+12
-14
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3 files changed

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‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2885,23 +2885,25 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
28852885
}
28862886
break;
28872887
case ISD::SRL:
2888+
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
2889+
28882890
if (const APInt *ShAmt = getValidShiftAmountConstant(Op, DemandedElts)) {
2889-
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
28902891
unsigned Shift = ShAmt->getZExtValue();
28912892
Known.Zero.lshrInPlace(Shift);
28922893
Known.One.lshrInPlace(Shift);
28932894
// High bits are known zero.
28942895
Known.Zero.setHighBits(Shift);
2895-
} else if (const APInt *ShMinAmt =
2896-
getValidMinimumShiftAmountConstant(Op, DemandedElts)) {
2897-
// Minimum shift high bits are known zero.
2898-
Known.Zero.setHighBits(ShMinAmt->getZExtValue());
2899-
} else {
2900-
// No matter the shift amount, the leading zeros will stay zero.
2901-
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
2902-
Known.Zero = APInt::getHighBitsSet(BitWidth, Known.countMinLeadingZeros());
2903-
Known.One.clearAllBits();
2896+
break;
29042897
}
2898+
2899+
// No matter the shift amount, the leading zeros will stay zero.
2900+
Known.Zero = APInt::getHighBitsSet(BitWidth, Known.countMinLeadingZeros());
2901+
Known.One.clearAllBits();
2902+
2903+
// Minimum shift high bits are known zero.
2904+
if (const APInt *ShMinAmt =
2905+
getValidMinimumShiftAmountConstant(Op, DemandedElts))
2906+
Known.Zero.setHighBits(ShMinAmt->getZExtValue());
29052907
break;
29062908
case ISD::SRA:
29072909
if (const APInt *ShAmt = getValidShiftAmountConstant(Op, DemandedElts)) {

‎llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -405,7 +405,6 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
405405
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0]
406406
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
407407
; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm2, %zmm1
408-
; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
409408
; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
410409
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
411410
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
@@ -923,7 +922,6 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
923922
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0]
924923
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
925924
; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm2, %zmm1
926-
; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
927925
; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1
928926
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
929927
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1

‎llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -345,7 +345,6 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
345345
; AVX512BW: # %bb.0:
346346
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
347347
; AVX512BW-NEXT: vpsrlvw {{.*}}(%rip), %zmm1, %zmm1
348-
; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
349348
; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
350349
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
351350
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
@@ -793,7 +792,6 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
793792
; AVX512BW: # %bb.0:
794793
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
795794
; AVX512BW-NEXT: vpsrlvw {{.*}}(%rip), %zmm1, %zmm1
796-
; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
797795
; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
798796
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
799797
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1

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