@@ -305,8 +305,6 @@ void parallel_master_allocate() {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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- // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8
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- // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
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// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -316,24 +314,17 @@ void parallel_master_allocate() {
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// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
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// CHECK1: omp_if.then:
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// CHECK1-NEXT: invoke void @_Z3foov()
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- // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD :%.*]]
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+ // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD :%.*]]
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// CHECK1: invoke.cont:
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// CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
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// CHECK1-NEXT: br label [[OMP_IF_END]]
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- // CHECK1: lpad:
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+ // CHECK1: omp_if.end:
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+ // CHECK1-NEXT: ret void
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+ // CHECK1: terminate.lpad:
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// CHECK1-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 }
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// CHECK1-NEXT: catch i8* null
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// CHECK1-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0
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- // CHECK1-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8
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- // CHECK1-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1
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- // CHECK1-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4
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- // CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
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- // CHECK1-NEXT: br label [[TERMINATE_HANDLER:%.*]]
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- // CHECK1: omp_if.end:
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- // CHECK1-NEXT: ret void
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- // CHECK1: terminate.handler:
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- // CHECK1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8
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- // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6:[0-9]+]]
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+ // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR6:[0-9]+]]
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// CHECK1-NEXT: unreachable
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//
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//
@@ -363,8 +354,6 @@ void parallel_master_allocate() {
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// CHECK2-NEXT: entry:
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// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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- // CHECK2-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8
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- // CHECK2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
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// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
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// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -374,24 +363,17 @@ void parallel_master_allocate() {
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// CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
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// CHECK2: omp_if.then:
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// CHECK2-NEXT: invoke void @_Z3foov()
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- // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD :%.*]]
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+ // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD :%.*]]
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// CHECK2: invoke.cont:
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// CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
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// CHECK2-NEXT: br label [[OMP_IF_END]]
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- // CHECK2: lpad:
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+ // CHECK2: omp_if.end:
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+ // CHECK2-NEXT: ret void
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+ // CHECK2: terminate.lpad:
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// CHECK2-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 }
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// CHECK2-NEXT: catch i8* null
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// CHECK2-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0
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- // CHECK2-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8
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- // CHECK2-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1
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- // CHECK2-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4
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- // CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
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- // CHECK2-NEXT: br label [[TERMINATE_HANDLER:%.*]]
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- // CHECK2: omp_if.end:
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- // CHECK2-NEXT: ret void
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- // CHECK2: terminate.handler:
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- // CHECK2-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8
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- // CHECK2-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6:[0-9]+]]
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+ // CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR6:[0-9]+]]
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// CHECK2-NEXT: unreachable
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//
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//
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