Add SPV_KHR_integer_dot_product support

Add support for mapping the SPV_KHR_integer_dot_product extension
operations to and from SPIR-V friendly IR.

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@faea0eb

Author: svenvh

llvm-spirv/include/LLVMSPIRVExtensions.inc

@@ -7,6 +7,7 @@ EXT(SPV_EXT_shader_atomic_float_min_max)
 EXT(SPV_KHR_no_integer_wrap_decoration)
 EXT(SPV_KHR_float_controls)
 EXT(SPV_KHR_linkonce_odr)
+EXT(SPV_KHR_integer_dot_product)
 EXT(SPV_INTEL_subgroups)
 EXT(SPV_INTEL_media_block_io)
 EXT(SPV_INTEL_device_side_avc_motion_estimation)

llvm-spirv/lib/SPIRV/SPIRVReader.cpp

@@ -3578,6 +3578,9 @@ Instruction *SPIRVToLLVM::transSPIRVBuiltinFromInst(SPIRVInstruction *BI,
   if (OC == OpImageSampleExplicitLod)
     AddRetTypePostfix = true;
 
+  if (OpSDotKHR <= BI->getOpCode() && BI->getOpCode() <= OpSUDotAccSatKHR)
+    AddRetTypePostfix = true;
+
   if (AddRetTypePostfix) {
     const Type *RetTy =
         BI->hasType() ? transType(BI->getType()) : Type::getVoidTy(*Context);

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h

@@ -2818,6 +2818,88 @@ class SPIRVExpectINTELInstBase : public SPIRVInstTemplateBase {
 _SPIRV_OP_INTERNAL(ExpectINTEL, true, 5)
 #undef _SPIRV_OP_INTERNAL
 
+class SPIRVDotKHRBase : public SPIRVInstTemplateBase {
+protected:
+  SPIRVCapVec getRequiredCapability() const override {
+    // Both vector operands must have the same type, so analyzing the
+    // first operand will suffice.
+    SPIRVCapabilityKind ArgCap = getRequiredCapabilityForOperand(Ops[0]);
+    return getVec(ArgCap, CapabilityDotProductKHR);
+  }
+
+  llvm::Optional<ExtensionID> getRequiredExtension() const override {
+    return ExtensionID::SPV_KHR_integer_dot_product;
+  }
+
+  void validate() const override {
+    SPIRVInstruction::validate();
+    SPIRVId Vec1 = Ops[0];
+    SPIRVId Vec2 = Ops[1];
+    (void)Vec1;
+    (void)Vec2;
+
+    assert(getValueType(Vec1) == getValueType(Vec2) &&
+           "Input vectors must have the same type");
+    assert(getType()->isTypeInt() && "Result type must be an integer type");
+    assert(!getType()->isTypeVector() && "Result type must be scalar");
+  }
+
+private:
+  bool isAccSat() const {
+    return (OpCode == OpSDotAccSatKHR || OpCode == OpUDotAccSatKHR ||
+            OpCode == OpSUDotAccSatKHR);
+  }
+
+  Optional<PackedVectorFormat> getPackedVectorFormat() const {
+    size_t PackFmtIdx = 2;
+    if (isAccSat()) {
+      // AccSat instructions have an additional Accumulator operand.
+      PackFmtIdx++;
+    }
+
+    if (PackFmtIdx == Ops.size() - 1)
+      return static_cast<PackedVectorFormat>(Ops[PackFmtIdx]);
+
+    return None;
+  }
+
+  SPIRVCapabilityKind getRequiredCapabilityForOperand(SPIRVId ArgId) const {
+    const SPIRVType *T = getValueType(ArgId);
+    if (auto PackFmt = getPackedVectorFormat()) {
+      switch (*PackFmt) {
+      case PackedVectorFormatPackedVectorFormat4x8BitKHR:
+        assert(!T->isTypeVector() && T->isTypeInt() && T->getBitWidth() == 32 &&
+               "Type does not match pack format");
+        return CapabilityDotProductInput4x8BitPackedKHR;
+      case PackedVectorFormatMax:
+        break;
+      }
+      llvm_unreachable("Unknown Packed Vector Format");
+    }
+
+    if (T->isTypeVector()) {
+      const SPIRVType *EltT = T->getVectorComponentType();
+      if (T->getVectorComponentCount() == 4 && EltT->isTypeInt() &&
+          EltT->getBitWidth() == 8)
+        return CapabilityDotProductInput4x8BitKHR;
+      if (EltT->isTypeInt())
+        return CapabilityDotProductInputAllKHR;
+    }
+
+    llvm_unreachable("No mapping for argument type to capability.");
+  }
+};
+
+#define _SPIRV_OP(x, ...)                                                      \
+  typedef SPIRVInstTemplate<SPIRVDotKHRBase, Op##x, __VA_ARGS__> SPIRV##x;
+_SPIRV_OP(SDotKHR, true, 5, true, 2)
+_SPIRV_OP(UDotKHR, true, 5, true, 2)
+_SPIRV_OP(SUDotKHR, true, 5, true, 2)
+_SPIRV_OP(SDotAccSatKHR, true, 6, true, 3)
+_SPIRV_OP(UDotAccSatKHR, true, 6, true, 3)
+_SPIRV_OP(SUDotAccSatKHR, true, 6, true, 3)
+#undef _SPIRV_OP
+
 class SPIRVSubgroupShuffleINTELInstBase : public SPIRVInstTemplateBase {
 protected:
   SPIRVCapVec getRequiredCapability() const override {

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h

@@ -327,6 +327,12 @@ _SPIRV_OP(GroupNonUniformBitwiseXor, 361)
 _SPIRV_OP(GroupNonUniformLogicalAnd, 362)
 _SPIRV_OP(GroupNonUniformLogicalOr, 363)
 _SPIRV_OP(GroupNonUniformLogicalXor, 364)
+_SPIRV_OP(SDotKHR, 4450)
+_SPIRV_OP(UDotKHR, 4451)
+_SPIRV_OP(SUDotKHR, 4452)
+_SPIRV_OP(SDotAccSatKHR, 4453)
+_SPIRV_OP(UDotAccSatKHR, 4454)
+_SPIRV_OP(SUDotAccSatKHR, 4455)
 _SPIRV_OP(SubgroupShuffleINTEL, 5571)
 _SPIRV_OP(SubgroupShuffleDownINTEL, 5572)
 _SPIRV_OP(SubgroupShuffleUpINTEL, 5573)