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[DebugInfo][InstrRef] Instrument x86 CMOV conversion to preserve variable values
X86's CMOV conversion transforms CMOV instructions into control flow between blocks, meaning the value is computed by a PHI rather than a "real" machine instruction. In instruction-referencing mode, we need to transfer the instruction label between the old CMOV and the new PHI instruction to mark where the variable value is computed. There's an extra complication in that memory operands can be unfolded from the CMOV and sunk into the new blocks -- the test checks both scenarios where the instruction number has to hop between instructions. This omission exposed by Dexter testing. Reviewed By: Orlando Differential Revision: https://reviews.llvm.org/D145565
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‎llvm/lib/Target/X86/X86CmovConversion.cpp

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@@ -774,6 +774,8 @@ void X86CmovConverterPass::convertCmovInstsToBranches(
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const TargetRegisterClass *RC = MRI->getRegClass(MI.getOperand(0).getReg());
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Register TmpReg = MRI->createVirtualRegister(RC);
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// Retain debug instr number when unfolded.
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unsigned OldDebugInstrNum = MI.peekDebugInstrNum();
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SmallVector<MachineInstr *, 4> NewMIs;
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bool Unfolded = TII->unfoldMemoryOperand(*MBB->getParent(), MI, TmpReg,
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/*UnfoldLoad*/ true,
@@ -791,6 +793,9 @@ void X86CmovConverterPass::convertCmovInstsToBranches(
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if (&*MIItBegin == &MI)
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MIItBegin = MachineBasicBlock::iterator(NewCMOV);
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if (OldDebugInstrNum)
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NewCMOV->setDebugInstrNum(OldDebugInstrNum);
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// Sink whatever instructions were needed to produce the unfolded operand
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// into the false block.
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for (auto *NewMI : NewMIs) {
@@ -858,6 +863,11 @@ void X86CmovConverterPass::convertCmovInstsToBranches(
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LLVM_DEBUG(dbgs() << "\tFrom: "; MIIt->dump());
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LLVM_DEBUG(dbgs() << "\tTo: "; MIB->dump());
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// debug-info: we can just copy the instr-ref number from one instruction
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// to the other, seeing how it's a one-for-one substitution.
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if (unsigned InstrNum = MIIt->peekDebugInstrNum())
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MIB->setDebugInstrNum(InstrNum);
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// Add this PHI to the rewrite table.
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RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
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}

‎llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir

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@@ -0,0 +1,192 @@
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# RUN: llc %s -o - --run-pass=x86-cmov-conversion -mtriple=x86_64-- | FileCheck %s
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# REQUIRES: x86-registered-target
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#
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# Check that when we create new blocks and PHIs to represent CMOVs, that the
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# debug-instr-number is replaced on the new instruction, to preserve variable
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# locations. Check that this still works when unfolding memory operands, which
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# involves more decomposition of instructions.
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#
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# CHECK-LABEL: name: CmovInHotPath
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# CHECK-LABEL: bb.3.for.body:
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# CHECK: CMOV32rr {{.*}}, debug-instr-number 1
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#
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# CHECK-LABEL: name: test_cmov_memoperand_in_group_reuse_for_addr2
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# CHECK-LABEL: bb.2.entry:
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# CHECK-NEXT: PHI {{.*}} debug-instr-number 1,
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# CHECK-NEXT: PHI {{.*}} debug-instr-number 2,
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--- |
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; ModuleID = 'x86-cmov-converter.ll'
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source_filename = "x86-cmov-converter.ll"
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare void @llvm.dbg.value(metadata, metadata, metadata) #0
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define void @CmovInHotPath(i32 %n, i32 %a, i32 %b, ptr nocapture %c, ptr nocapture readnone %d) !dbg !7 {
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entry:
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%cmp14 = icmp sgt i32 %n, 0, !dbg !12
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br i1 %cmp14, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%wide.trip.count = zext i32 %n to i64, !dbg !13
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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ret void
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for.body: ; preds = %for.body, %for.body.preheader
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%lsr.iv1 = phi ptr [ %uglygep, %for.body ], [ %c, %for.body.preheader ]
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%lsr.iv = phi i64 [ %lsr.iv.next, %for.body ], [ %wide.trip.count, %for.body.preheader ]
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%0 = load i32, ptr %lsr.iv1, align 4, !dbg !13
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%add = add nsw i32 %0, 1, !dbg !13
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%mul = mul nsw i32 %0, %a, !dbg !13
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%cmp3 = icmp sgt i32 %mul, %b, !dbg !13
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%. = select i1 %cmp3, i32 10, i32 %add, !dbg !13
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call void @llvm.dbg.value(metadata i32 %., metadata !14, metadata !DIExpression()), !dbg !13
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%mul7 = mul nsw i32 %., %add, !dbg !13
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store i32 %mul7, ptr %lsr.iv1, align 4, !dbg !13
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%lsr.iv.next = add nsw i64 %lsr.iv, -1, !dbg !13
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%uglygep = getelementptr i8, ptr %lsr.iv1, i64 4, !dbg !13
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%exitcond = icmp eq i64 %lsr.iv.next, 0, !dbg !13
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br i1 %exitcond, label %for.cond.cleanup, label %for.body, !dbg !13
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}
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define i32 @test_cmov_memoperand_in_group_reuse_for_addr2(i32 %a, i32 %b, ptr %x, ptr %y) !dbg !15 {
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entry:
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%cond = icmp ugt i32 %a, %b, !dbg !16
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%load1 = load ptr, ptr %y, align 8, !dbg !16
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%p = select i1 %cond, ptr %x, ptr %load1, !dbg !16
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call void @llvm.dbg.value(metadata ptr %p, metadata !17, metadata !DIExpression()), !dbg !16
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%load2 = load i32, ptr %p, align 4, !dbg !16
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%z = select i1 %cond, i32 %a, i32 %load2, !dbg !16
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call void @llvm.dbg.value(metadata i32 %z, metadata !18, metadata !DIExpression()), !dbg !16
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ret i32 %z, !dbg !16
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}
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attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!3, !4, !5}
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!llvm.ident = !{!6}
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!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
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!1 = !DIFile(filename: "test.c", directory: "/tmp/out.c")
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!2 = !{}
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!3 = !{i32 7, !"Dwarf Version", i32 4}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = !{i32 1, !"wchar_size", i32 4}
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!6 = !{!""}
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!7 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !8, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
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!8 = !DISubroutineType(types: !9)
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!9 = !{!10, !11, !11}
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!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
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!11 = !DIBasicType(name: "long int", size: 64, encoding: DW_ATE_signed)
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!12 = !DILocation(line: 16, column: 3, scope: !7)
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!13 = !DILocation(line: 15, column: 3, scope: !7)
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!14 = !DILocalVariable(name: "bar", arg: 1, scope: !7, file: !1, line: 3, type: !11)
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!15 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !8, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
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!16 = !DILocation(line: 16, column: 3, scope: !15)
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!17 = !DILocalVariable(name: "bar", arg: 1, scope: !15, file: !1, line: 3, type: !11)
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!18 = !DILocalVariable(name: "baz", arg: 2, scope: !15, file: !1, line: 3, type: !11)
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...
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---
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name: CmovInHotPath
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tracksRegLiveness: true
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debugInstrRef: true
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registers:
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- { id: 0, class: gr64, preferred-register: '' }
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- { id: 1, class: gr64, preferred-register: '' }
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- { id: 2, class: gr64, preferred-register: '' }
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- { id: 3, class: gr64, preferred-register: '' }
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- { id: 4, class: gr64, preferred-register: '' }
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- { id: 5, class: gr32, preferred-register: '' }
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- { id: 6, class: gr32, preferred-register: '' }
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- { id: 7, class: gr32, preferred-register: '' }
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liveins:
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- { reg: '$edi', virtual-reg: '%5' }
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- { reg: '$esi', virtual-reg: '%6' }
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- { reg: '$edx', virtual-reg: '%7' }
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- { reg: '$rcx', virtual-reg: '%8' }
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x50000000), %bb.2(0x30000000)
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liveins: $edi, $esi, $edx, $rcx
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%8:gr64 = COPY $rcx
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%7:gr32 = COPY $edx
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%6:gr32 = COPY $esi
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%5:gr32 = COPY $edi
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TEST32rr %5, %5, implicit-def $eflags, debug-location !12
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JCC_1 %bb.2, 14, implicit $eflags
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JMP_1 %bb.1
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bb.1.for.body.preheader:
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successors: %bb.3(0x80000000)
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%10:gr32 = MOV32rr %5, debug-location !13
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%0:gr64 = SUBREG_TO_REG 0, killed %10, %subreg.sub_32bit, debug-location !13
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JMP_1 %bb.3
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bb.2.for.cond.cleanup:
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RET 0
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bb.3.for.body:
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successors: %bb.2(0x04000000), %bb.3(0x7c000000)
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%1:gr64 = PHI %8, %bb.1, %4, %bb.3
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%2:gr64 = PHI %0, %bb.1, %3, %bb.3
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%11:gr32 = MOV32rm %1, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s32) from %ir.lsr.iv1)
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%12:gr32 = nsw INC32r %11, implicit-def dead $eflags, debug-location !13
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%13:gr32 = nsw IMUL32rr %11, %6, implicit-def dead $eflags, debug-location !13
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%14:gr32 = SUB32rr %13, %7, implicit-def $eflags, debug-location !13
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%15:gr32 = MOV32ri 10
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%16:gr32 = CMOV32rr %12, killed %15, 15, implicit $eflags, debug-instr-number 1, debug-location !13
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DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !13
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%17:gr32 = nsw IMUL32rr %16, %12, implicit-def dead $eflags, debug-location !13
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MOV32mr %1, 1, $noreg, 0, $noreg, killed %17, debug-location !13 :: (store (s32) into %ir.lsr.iv1)
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%4:gr64 = ADD64ri8 %1, 4, implicit-def dead $eflags, debug-location !13
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%3:gr64 = DEC64r %2, implicit-def $eflags, debug-location !13
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JCC_1 %bb.2, 4, implicit $eflags, debug-location !13
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JMP_1 %bb.3, debug-location !13
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...
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---
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name: test_cmov_memoperand_in_group_reuse_for_addr2
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alignment: 16
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tracksRegLiveness: true
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debugInstrRef: true
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registers:
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- { id: 0, class: gr32, preferred-register: '' }
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- { id: 1, class: gr32, preferred-register: '' }
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- { id: 2, class: gr64, preferred-register: '' }
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- { id: 3, class: gr64, preferred-register: '' }
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- { id: 4, class: gr32, preferred-register: '' }
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- { id: 5, class: gr64, preferred-register: '' }
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- { id: 6, class: gr32, preferred-register: '' }
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liveins:
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- { reg: '$edi', virtual-reg: '%0' }
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- { reg: '$esi', virtual-reg: '%1' }
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- { reg: '$rdx', virtual-reg: '%2' }
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- { reg: '$rcx', virtual-reg: '%3' }
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $edi, $esi, $rdx, $rcx
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%3:gr64 = COPY $rcx
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%2:gr64 = COPY $rdx
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%1:gr32 = COPY $esi
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%0:gr32 = COPY $edi
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%4:gr32 = SUB32rr %0, %1, implicit-def $eflags, debug-location !16
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%5:gr64 = CMOV64rm %2, %3, 1, $noreg, 0, $noreg, 6, implicit $eflags, debug-instr-number 1, debug-location !16 :: (load (s64) from %ir.y)
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DBG_INSTR_REF !17, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !16
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%6:gr32 = CMOV32rm %0, killed %5, 1, $noreg, 0, $noreg, 6, implicit $eflags, debug-instr-number 2, debug-location !16 :: (load (s32) from %ir.p)
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DBG_INSTR_REF !18, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !16
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$eax = COPY %6, debug-location !16
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RET 0, $eax, debug-location !16
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...

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