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Merge from 'main' to 'sycl-web' (1 commits)
 CONFLICT (content): Merge conflict in llvm/include/llvm/IR/Intrinsics.h CONFLICT (content): Merge conflict in llvm/include/llvm/IR/Intrinsics.td CONFLICT (content): Merge conflict in llvm/lib/IR/Function.cpp
2 parents 72f55c7 + 4136e08 commit b294d5a

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5 files changed

+39
-145
lines changed

5 files changed

+39
-145
lines changed

‎llvm/include/llvm/IR/Intrinsics.h

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -130,16 +130,15 @@ namespace Intrinsic {
130130
SameVecWidthArgument,
131131
#ifndef INTEL_SYCL_OPAQUEPOINTER_READY
132132
PtrToArgument,
133-
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
134133
PtrToElt,
134+
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
135135
VecOfAnyPtrsToElt,
136136
VecElementArgument,
137137
Subdivide2Argument,
138138
Subdivide4Argument,
139139
VecOfBitcastsToInt,
140140
AMX,
141141
PPCQuad,
142-
AnyPtrToElt,
143142
AArch64Svcount,
144143
} Kind;
145144

@@ -162,11 +161,7 @@ namespace Intrinsic {
162161
unsigned getArgumentNumber() const {
163162
assert(Kind == Argument || Kind == ExtendArgument ||
164163
Kind == TruncArgument || Kind == HalfVecArgument ||
165-
Kind == SameVecWidthArgument ||
166-
#ifndef INTEL_SYCL_OPAQUEPOINTER_READY
167-
Kind == PtrToArgument ||
168-
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
169-
Kind == PtrToElt || Kind == VecElementArgument ||
164+
Kind == SameVecWidthArgument || Kind == VecElementArgument ||
170165
Kind == Subdivide2Argument || Kind == Subdivide4Argument ||
171166
Kind == VecOfBitcastsToInt);
172167
return Argument_Info >> 3;
@@ -183,15 +178,14 @@ namespace Intrinsic {
183178
return (ArgKind)(Argument_Info & 7);
184179
}
185180

186-
// VecOfAnyPtrsToElt and AnyPtrToElt uses both an overloaded argument (for
187-
// address space) and a reference argument (for matching vector width and
188-
// element types)
181+
// VecOfAnyPtrsToElt uses both an overloaded argument (for address space)
182+
// and a reference argument (for matching vector width and element types)
189183
unsigned getOverloadArgNumber() const {
190-
assert(Kind == VecOfAnyPtrsToElt || Kind == AnyPtrToElt);
184+
assert(Kind == VecOfAnyPtrsToElt);
191185
return Argument_Info >> 16;
192186
}
193187
unsigned getRefArgNumber() const {
194-
assert(Kind == VecOfAnyPtrsToElt || Kind == AnyPtrToElt);
188+
assert(Kind == VecOfAnyPtrsToElt);
195189
return Argument_Info & 0xFFFF;
196190
}
197191

‎llvm/include/llvm/IR/Intrinsics.td

Lines changed: 4 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -294,10 +294,6 @@ def IIT_V1 : IIT_Vec<1, 28>;
294294
def IIT_VARARG : IIT_VT<isVoid, 29>;
295295
def IIT_HALF_VEC_ARG : IIT_Base<30>;
296296
def IIT_SAME_VEC_WIDTH_ARG : IIT_Base<31>;
297-
#ifndef INTEL_SYCL_OPAQUEPOINTER_READY
298-
def IIT_PTR_TO_ARG : IIT_Base<32>;
299-
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
300-
def IIT_PTR_TO_ELT : IIT_Base<33>;
301297
def IIT_VEC_OF_ANYPTRS_TO_ELT : IIT_Base<34>;
302298
def IIT_I128 : IIT_Int<128, 35>;
303299
def IIT_V512 : IIT_Vec<512, 36>;
@@ -320,7 +316,6 @@ def IIT_PPCF128 : IIT_VT<ppcf128, 52>;
320316
def IIT_V3 : IIT_Vec<3, 53>;
321317
def IIT_EXTERNREF : IIT_VT<externref, 54>;
322318
def IIT_FUNCREF : IIT_VT<funcref, 55>;
323-
def IIT_ANYPTR_TO_ELT : IIT_Base<56>;
324319
def IIT_I2 : IIT_Int<2, 57>;
325320
def IIT_I4 : IIT_Int<4, 58>;
326321
def IIT_AARCH64_SVCOUNT : IIT_VT<aarch64svcount, 59>;
@@ -451,12 +446,6 @@ class LLVMScalarOrSameVectorWidth<int idx, LLVMType elty>
451446
], elty.Sig);
452447
}
453448

454-
#ifndef INTEL_SYCL_OPAQUEPOINTER_READY
455-
class LLVMPointerTo<int num> : LLVMMatchType<num, IIT_PTR_TO_ARG>;
456-
#endif // INTEL_SYCL_OPAQUEPOINTER_READY
457-
class LLVMPointerToElt<int num> : LLVMMatchType<num, IIT_PTR_TO_ELT>;
458-
class LLVMAnyPointerToElt<int num>
459-
: LLVMMatchTypeNextArg<num, IIT_ANYPTR_TO_ELT>;
460449
class LLVMVectorOfAnyPointersToElt<int num>
461450
: LLVMMatchTypeNextArg<num, IIT_VEC_OF_ANYPTRS_TO_ELT>;
462451
class LLVMVectorElementType<int num> : LLVMMatchType<num, IIT_VEC_ELEMENT>;
@@ -2310,13 +2299,13 @@ def int_masked_scatter:
23102299

23112300
def int_masked_expandload:
23122301
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
2313-
[LLVMPointerToElt<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
2302+
[llvm_ptr_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
23142303
LLVMMatchType<0>],
23152304
[IntrReadMem, IntrWillReturn, NoCapture<ArgIndex<0>>]>;
23162305

23172306
def int_masked_compressstore:
23182307
DefaultAttrsIntrinsic<[],
2319-
[llvm_anyvector_ty, LLVMPointerToElt<0>,
2308+
[llvm_anyvector_ty, llvm_ptr_ty,
23202309
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
23212310
[IntrWriteMem, IntrArgMemOnly, IntrWillReturn,
23222311
NoCapture<ArgIndex<1>>]>;
@@ -2455,15 +2444,15 @@ def int_matrix_multiply
24552444

24562445
def int_matrix_column_major_load
24572446
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
2458-
[LLVMPointerToElt<0>, llvm_anyint_ty, llvm_i1_ty,
2447+
[llvm_ptr_ty, llvm_anyint_ty, llvm_i1_ty,
24592448
llvm_i32_ty, llvm_i32_ty],
24602449
[IntrNoSync, IntrWillReturn, IntrArgMemOnly, IntrReadMem,
24612450
NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>,
24622451
ImmArg<ArgIndex<4>>]>;
24632452

24642453
def int_matrix_column_major_store
24652454
: DefaultAttrsIntrinsic<[],
2466-
[llvm_anyvector_ty, LLVMPointerToElt<0>,
2455+
[llvm_anyvector_ty, llvm_ptr_ty,
24672456
llvm_anyint_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty],
24682457
[IntrNoSync, IntrWillReturn, IntrArgMemOnly, IntrWriteMem,
24692458
WriteOnly<ArgIndex<1>>, NoCapture<ArgIndex<1>>,

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 15 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -956,59 +956,53 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
956956

957957
class AdvSIMD_1Vec_PredLoad_Intrinsic
958958
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
959-
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
960-
LLVMPointerToElt<0>],
959+
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty],
961960
[IntrReadMem, IntrArgMemOnly]>;
962961

963962
class AdvSIMD_2Vec_PredLoad_Intrinsic
964963
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
965-
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
966-
LLVMPointerToElt<0>],
964+
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty],
967965
[IntrReadMem, IntrArgMemOnly]>;
968966

969967
class AdvSIMD_3Vec_PredLoad_Intrinsic
970968
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
971-
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
972-
LLVMPointerToElt<0>],
969+
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty],
973970
[IntrReadMem, IntrArgMemOnly]>;
974971

975972
class AdvSIMD_4Vec_PredLoad_Intrinsic
976973
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>,
977974
LLVMMatchType<0>],
978-
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
979-
LLVMPointerToElt<0>],
975+
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty],
980976
[IntrReadMem, IntrArgMemOnly]>;
981977

982978
class AdvSIMD_1Vec_PredLoad_WriteFFR_Intrinsic
983979
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
984-
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
985-
LLVMPointerToElt<0>],
980+
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty],
986981
[IntrInaccessibleMemOrArgMemOnly]>;
987982

988983
class AdvSIMD_1Vec_PredStore_Intrinsic
989984
: DefaultAttrsIntrinsic<[],
990985
[llvm_anyvector_ty,
991-
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
992-
LLVMPointerToElt<0>],
986+
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty],
993987
[IntrArgMemOnly, NoCapture<ArgIndex<2>>]>;
994988

995989
class AdvSIMD_2Vec_PredStore_Intrinsic
996990
: DefaultAttrsIntrinsic<[],
997991
[llvm_anyvector_ty, LLVMMatchType<0>,
998-
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>],
992+
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty],
999993
[IntrArgMemOnly, NoCapture<ArgIndex<3>>]>;
1000994

1001995
class AdvSIMD_3Vec_PredStore_Intrinsic
1002996
: DefaultAttrsIntrinsic<[],
1003997
[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>,
1004-
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>],
998+
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty],
1005999
[IntrArgMemOnly, NoCapture<ArgIndex<4>>]>;
10061000

10071001
class AdvSIMD_4Vec_PredStore_Intrinsic
10081002
: DefaultAttrsIntrinsic<[],
10091003
[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>,
10101004
LLVMMatchType<0>,
1011-
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>],
1005+
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty],
10121006
[IntrArgMemOnly, NoCapture<ArgIndex<5>>]>;
10131007

10141008
class AdvSIMD_SVE_Index_Intrinsic
@@ -1422,7 +1416,7 @@ class AdvSIMD_GatherLoad_SV_64b_Offsets_Intrinsic
14221416
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
14231417
[
14241418
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
1425-
LLVMPointerToElt<0>,
1419+
llvm_ptr_ty,
14261420
LLVMScalarOrSameVectorWidth<0, llvm_i64_ty>
14271421
],
14281422
[IntrReadMem, IntrArgMemOnly]>;
@@ -1431,7 +1425,7 @@ class AdvSIMD_GatherLoad_SV_64b_Offsets_WriteFFR_Intrinsic
14311425
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
14321426
[
14331427
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
1434-
LLVMPointerToElt<0>,
1428+
llvm_ptr_ty,
14351429
LLVMScalarOrSameVectorWidth<0, llvm_i64_ty>
14361430
],
14371431
[IntrInaccessibleMemOrArgMemOnly]>;
@@ -1440,7 +1434,7 @@ class AdvSIMD_GatherLoad_SV_32b_Offsets_Intrinsic
14401434
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
14411435
[
14421436
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
1443-
LLVMPointerToElt<0>,
1437+
llvm_ptr_ty,
14441438
LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>
14451439
],
14461440
[IntrReadMem, IntrArgMemOnly]>;
@@ -1449,7 +1443,7 @@ class AdvSIMD_GatherLoad_SV_32b_Offsets_WriteFFR_Intrinsic
14491443
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
14501444
[
14511445
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
1452-
LLVMPointerToElt<0>,
1446+
llvm_ptr_ty,
14531447
LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>
14541448
],
14551449
[IntrInaccessibleMemOrArgMemOnly]>;
@@ -1477,7 +1471,7 @@ class AdvSIMD_ScatterStore_SV_64b_Offsets_Intrinsic
14771471
[
14781472
llvm_anyvector_ty,
14791473
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
1480-
LLVMPointerToElt<0>,
1474+
llvm_ptr_ty,
14811475
LLVMScalarOrSameVectorWidth<0, llvm_i64_ty>
14821476
],
14831477
[IntrWriteMem, IntrArgMemOnly]>;
@@ -1487,7 +1481,7 @@ class AdvSIMD_ScatterStore_SV_32b_Offsets_Intrinsic
14871481
[
14881482
llvm_anyvector_ty,
14891483
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
1490-
LLVMPointerToElt<0>,
1484+
llvm_ptr_ty,
14911485
LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>
14921486
],
14931487
[IntrWriteMem, IntrArgMemOnly]>;

‎llvm/include/llvm/IR/IntrinsicsRISCV.td

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1006,7 +1006,7 @@ let TargetPrefix = "riscv" in {
10061006
: DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
10071007
!add(nf, -1))),
10081008
!listconcat(!listsplat(LLVMMatchType<0>, nf),
1009-
[LLVMPointerToElt<0>, llvm_anyint_ty]),
1009+
[llvm_ptr_ty, llvm_anyint_ty]),
10101010
[NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic {
10111011
let VLOperand = !add(nf, 1);
10121012
}
@@ -1016,7 +1016,7 @@ let TargetPrefix = "riscv" in {
10161016
: DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
10171017
!add(nf, -1))),
10181018
!listconcat(!listsplat(LLVMMatchType<0>, nf),
1019-
[LLVMPointerToElt<0>,
1019+
[llvm_ptr_ty,
10201020
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
10211021
llvm_anyint_ty, LLVMMatchType<1>]),
10221022
[ImmArg<ArgIndex<!add(nf, 3)>>, NoCapture<ArgIndex<nf>>, IntrReadMem]>,
@@ -1033,7 +1033,7 @@ let TargetPrefix = "riscv" in {
10331033
: DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
10341034
!add(nf, -1)), [llvm_anyint_ty]),
10351035
!listconcat(!listsplat(LLVMMatchType<0>, nf),
1036-
[LLVMPointerToElt<0>, LLVMMatchType<1>]),
1036+
[llvm_ptr_ty, LLVMMatchType<1>]),
10371037
[NoCapture<ArgIndex<nf>>]>, RISCVVIntrinsic {
10381038
let VLOperand = !add(nf, 1);
10391039
}
@@ -1046,7 +1046,7 @@ let TargetPrefix = "riscv" in {
10461046
: DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
10471047
!add(nf, -1)), [llvm_anyint_ty]),
10481048
!listconcat(!listsplat(LLVMMatchType<0>, nf),
1049-
[LLVMPointerToElt<0>,
1049+
[llvm_ptr_ty,
10501050
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
10511051
LLVMMatchType<1>, LLVMMatchType<1>]),
10521052
[ImmArg<ArgIndex<!add(nf, 3)>>, NoCapture<ArgIndex<nf>>]>,
@@ -1060,7 +1060,7 @@ let TargetPrefix = "riscv" in {
10601060
: DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
10611061
!add(nf, -1))),
10621062
!listconcat(!listsplat(LLVMMatchType<0>, nf),
1063-
[LLVMPointerToElt<0>, llvm_anyint_ty, LLVMMatchType<1>]),
1063+
[llvm_ptr_ty, llvm_anyint_ty, LLVMMatchType<1>]),
10641064
[NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic {
10651065
let VLOperand = !add(nf, 2);
10661066
}
@@ -1070,7 +1070,7 @@ let TargetPrefix = "riscv" in {
10701070
: DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
10711071
!add(nf, -1))),
10721072
!listconcat(!listsplat(LLVMMatchType<0>, nf),
1073-
[LLVMPointerToElt<0>,
1073+
[llvm_ptr_ty,
10741074
llvm_anyint_ty,
10751075
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
10761076
LLVMMatchType<1>, LLVMMatchType<1>]),
@@ -1085,7 +1085,7 @@ let TargetPrefix = "riscv" in {
10851085
: DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
10861086
!add(nf, -1))),
10871087
!listconcat(!listsplat(LLVMMatchType<0>, nf),
1088-
[LLVMPointerToElt<0>, llvm_anyvector_ty, llvm_anyint_ty]),
1088+
[llvm_ptr_ty, llvm_anyvector_ty, llvm_anyint_ty]),
10891089
[NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic {
10901090
let VLOperand = !add(nf, 2);
10911091
}
@@ -1095,7 +1095,7 @@ let TargetPrefix = "riscv" in {
10951095
: DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
10961096
!add(nf, -1))),
10971097
!listconcat(!listsplat(LLVMMatchType<0>, nf),
1098-
[LLVMPointerToElt<0>,
1098+
[llvm_ptr_ty,
10991099
llvm_anyvector_ty,
11001100
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
11011101
llvm_anyint_ty, LLVMMatchType<2>]),
@@ -1110,7 +1110,7 @@ let TargetPrefix = "riscv" in {
11101110
: DefaultAttrsIntrinsic<[],
11111111
!listconcat([llvm_anyvector_ty],
11121112
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
1113-
[LLVMPointerToElt<0>, llvm_anyint_ty]),
1113+
[llvm_ptr_ty, llvm_anyint_ty]),
11141114
[NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
11151115
let VLOperand = !add(nf, 1);
11161116
}
@@ -1120,7 +1120,7 @@ let TargetPrefix = "riscv" in {
11201120
: DefaultAttrsIntrinsic<[],
11211121
!listconcat([llvm_anyvector_ty],
11221122
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
1123-
[LLVMPointerToElt<0>,
1123+
[llvm_ptr_ty,
11241124
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
11251125
llvm_anyint_ty]),
11261126
[NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
@@ -1133,7 +1133,7 @@ let TargetPrefix = "riscv" in {
11331133
: DefaultAttrsIntrinsic<[],
11341134
!listconcat([llvm_anyvector_ty],
11351135
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
1136-
[LLVMPointerToElt<0>, llvm_anyint_ty,
1136+
[llvm_ptr_ty, llvm_anyint_ty,
11371137
LLVMMatchType<1>]),
11381138
[NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
11391139
let VLOperand = !add(nf, 2);
@@ -1144,7 +1144,7 @@ let TargetPrefix = "riscv" in {
11441144
: DefaultAttrsIntrinsic<[],
11451145
!listconcat([llvm_anyvector_ty],
11461146
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
1147-
[LLVMPointerToElt<0>, llvm_anyint_ty,
1147+
[llvm_ptr_ty, llvm_anyint_ty,
11481148
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
11491149
LLVMMatchType<1>]),
11501150
[NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
@@ -1157,7 +1157,7 @@ let TargetPrefix = "riscv" in {
11571157
: DefaultAttrsIntrinsic<[],
11581158
!listconcat([llvm_anyvector_ty],
11591159
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
1160-
[LLVMPointerToElt<0>, llvm_anyvector_ty,
1160+
[llvm_ptr_ty, llvm_anyvector_ty,
11611161
llvm_anyint_ty]),
11621162
[NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
11631163
let VLOperand = !add(nf, 2);
@@ -1168,7 +1168,7 @@ let TargetPrefix = "riscv" in {
11681168
: DefaultAttrsIntrinsic<[],
11691169
!listconcat([llvm_anyvector_ty],
11701170
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
1171-
[LLVMPointerToElt<0>, llvm_anyvector_ty,
1171+
[llvm_ptr_ty, llvm_anyvector_ty,
11721172
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
11731173
llvm_anyint_ty]),
11741174
[NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {

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