@@ -1747,16 +1747,6 @@ block_load(AccessorT acc, detail::DeviceAccessorOffsetT byte_offset,
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return block_load<T, N>(detail::accessorToPointer<T>(acc, byte_offset),
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props);
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#else // !__ESIMD_FORCE_STATELESS_MEM
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- constexpr auto L1Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L1_key>(
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- cache_hint::none);
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- constexpr auto L2Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L2_key>(
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- cache_hint::none);
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- static_assert (!PropertyListT::template has_property<cache_hint_L3_key>(),
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- " L3 cache hint is reserved. The old/experimental L3 LSC cache "
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- " hint is cache_level::L2 now." );
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-
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// If the alignment property is not passed, then assume the pointer
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// is element-aligned.
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constexpr size_t DefaultAlignment = (sizeof (T) <= 4 ) ? 4 : sizeof (T);
@@ -1822,17 +1812,9 @@ __ESIMD_API std::enable_if_t<
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block_load (AccessorT acc, PropertyListT /* props */ = {}) {
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// Create new properties without the alignment property passed in 'props',
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// and add alignment<16> as it is usable and most favourable in this case.
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- constexpr auto L1Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L1_key>(
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- cache_hint::none);
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- constexpr auto L2Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L2_key>(
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- cache_hint::none);
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- static_assert (!PropertyListT::template has_property<cache_hint_L3_key>(),
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- " L3 cache hint is reserved. The old/experimental L3 LSC cache "
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- " hint is cache_level::L2 now." );
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- properties Props{cache_hint_L1<L1Hint>, cache_hint_L2<L2Hint>, alignment<16 >};
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- return block_load<T, N>(acc, 0 , Props);
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+ using NewPropertyListT =
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+ detail::add_or_replace_alignment_property_t <PropertyListT, 16 >;
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+ return block_load<T, N>(acc, 0 , NewPropertyListT{});
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}
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// / simd<T, N>
@@ -1877,18 +1859,8 @@ __ESIMD_API std::enable_if_t<
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block_load (AccessorT acc, detail::DeviceAccessorOffsetT byte_offset,
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simd_mask<1 > pred, simd<T, N> pass_thru,
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PropertyListT /* props */ = {}) {
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- constexpr auto L1Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L1_key>(
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- cache_hint::none);
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- constexpr auto L2Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L2_key>(
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- cache_hint::none);
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- static_assert (!PropertyListT::template has_property<cache_hint_L3_key>(),
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- " L3 cache hint is reserved. The old/experimental L3 LSC cache "
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- " hint is cache_level::L2 now." );
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-
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// If the alignment property is not passed, then assume the byte_offset
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- // is element-aligned and is at leat 4-bytes.
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+ // is element-aligned and is at least 4-bytes.
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constexpr size_t DefaultAlignment = (sizeof (T) <= 4 ) ? 4 : sizeof (T);
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using NewPropertyListT =
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detail::add_alignment_property_t <PropertyListT, DefaultAlignment>;
@@ -1980,17 +1952,9 @@ block_load(AccessorT acc, simd_mask<1> pred, simd<T, N> pass_thru,
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PropertyListT /* props */ = {}) {
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// Create new properties without the alignment property passed in 'props',
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// and add alignment<16> as it is usable and most favourable in this case.
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- constexpr auto L1Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L1_key>(
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- cache_hint::none);
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- constexpr auto L2Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L2_key>(
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- cache_hint::none);
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- static_assert (!PropertyListT::template has_property<cache_hint_L3_key>(),
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- " L3 cache hint is reserved. The old/experimental L3 LSC cache "
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- " hint is cache_level::L2 now." );
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- properties Props{cache_hint_L1<L1Hint>, cache_hint_L2<L2Hint>, alignment<16 >};
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- return block_load<T, N>(acc, 0 , pred, pass_thru, Props);
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+ using NewPropertyListT =
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+ detail::add_or_replace_alignment_property_t <PropertyListT, 16 >;
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+ return block_load<T, N>(acc, 0 , pred, pass_thru, NewPropertyListT{});
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}
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// / simd<T, N>
@@ -2030,19 +1994,10 @@ __ESIMD_API std::enable_if_t<
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block_load (AccessorT acc, simd_mask<1 > pred, PropertyListT /* props */ = {}) {
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// Create new properties without the alignment property passed in 'props',
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// and add alignment<16> as it is usable and most favourable in this case.
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- constexpr auto L1Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L1_key>(
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- cache_hint::none);
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- constexpr auto L2Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L2_key>(
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- cache_hint::none);
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- static_assert (!PropertyListT::template has_property<cache_hint_L3_key>(),
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- " L3 cache hint is reserved. The old/experimental L3 LSC cache "
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- " hint is cache_level::L2 now." );
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- properties Props{cache_hint_L1<L1Hint>, cache_hint_L2<L2Hint>, alignment<16 >};
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-
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+ using NewPropertyListT =
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+ detail::add_or_replace_alignment_property_t <PropertyListT, 16 >;
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simd<T, N> PassThru; // Intentionally uninitialized.
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- return block_load<T, N>(acc, 0 , pred, PassThru, Props );
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+ return block_load<T, N>(acc, 0 , pred, PassThru, NewPropertyListT{} );
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}
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// / Each of the following block store functions stores a contiguous memory block
@@ -2398,14 +2353,9 @@ __ESIMD_API std::enable_if_t<
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block_store (AccessorT acc, simd<T, N> vals, PropertyListT props = {}) {
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// Create new properties without the alignment property passed in 'props',
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// and add alignment<16> as it is usable and most favourable in this case.
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- constexpr auto L1Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L1_key>(
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- cache_hint::none);
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- constexpr auto L2Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L2_key>(
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- cache_hint::none);
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- properties Props{cache_hint_L1<L1Hint>, cache_hint_L2<L2Hint>, alignment<16 >};
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- block_store<T, N>(acc, 0 , vals, Props);
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+ using NewPropertyListT =
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+ detail::add_or_replace_alignment_property_t <PropertyListT, 16 >;
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+ block_store<T, N>(acc, 0 , vals, NewPropertyListT{});
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}
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// / void block_store(AccessorT acc, OffsetT byte_offset, // (acc-bs-3)
@@ -2490,14 +2440,9 @@ block_store(AccessorT acc, simd<T, N> vals, simd_mask<1> pred,
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PropertyListT props = {}) {
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// Create new properties without the alignment property passed in 'props',
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// and add alignment<16> as it is usable and most favourable in this case.
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- constexpr auto L1Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L1_key>(
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- cache_hint::none);
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- constexpr auto L2Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L2_key>(
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- cache_hint::none);
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- properties Props{cache_hint_L1<L1Hint>, cache_hint_L2<L2Hint>, alignment<16 >};
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- block_store<T, N>(acc, 0 , vals, pred, Props);
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+ using NewPropertyListT =
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+ detail::add_or_replace_alignment_property_t <PropertyListT, 16 >;
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+ block_store<T, N>(acc, 0 , vals, pred, NewPropertyListT{});
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}
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// / @} sycl_esimd_memory_block
@@ -7168,16 +7113,6 @@ atomic_update(AccessorTy acc, simd<Toffset, N> byte_offset, simd_mask<N> mask,
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return atomic_update<Op, T, N>(__ESIMD_DNS::accessorToPointer<T>(acc),
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byte_offset, mask, props);
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#else
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- constexpr auto L1Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L1_key>(
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- cache_hint::none);
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- constexpr auto L2Hint =
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- detail::getPropertyValue<PropertyListT, cache_hint_L2_key>(
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- cache_hint::none);
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- static_assert (!PropertyListT::template has_property<cache_hint_L3_key>(),
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- " L3 cache hint is reserved. The old/experimental L3 LSC cache "
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- " hint is cache_level::L2 now." );
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-
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static_assert (std::is_integral_v<Toffset>, " Unsupported offset type" );
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if constexpr (detail::has_cache_hints<PropertyListT>() ||
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