Merge remote-tracking branch 'intel_llvm/sycl' into jit_cache_2

Author: vladimirlaz

.github/CODEOWNERS

@@ -114,3 +114,8 @@ SYCLLowerIR/ @kbobrovs @DenisBakhvalov
 esimd/ @kbobrovs @DenisBakhvalov
 sycl/include/CL/sycl/INTEL/esimd.hpp @kbobrovs @DenisBakhvalov
 sycl/doc/extensions/ExplicitSIMD/ @kbobrovs
+
+# ITT annotations
+llvm/lib/Transforms/Instrumentation/SPIRITTAnnotations.cpp @MrSidims
+llvm/include/llvm/Transforms/Instrumentation/SPIRITTAnnotations.h @MrSidims
+

buildbot/dependency.conf

@@ -1,11 +1,11 @@
 [VERSIONS]
-# https://github.com/intel/llvm/releases/download/2021-WW10/oclcpuexp-2021.11.3.0.02_rel.tar.gz
-ocl_cpu_rt_ver=2021.11.3.0.02
-# https://github.com/intel/llvm/releases/download/2021-WW10/win-oclcpuexp-2021.11.3.0.02_rel.zip
-ocl_cpu_rt_ver_win=2021.11.3.0.02
+# https://github.com/intel/llvm/releases/download/2021-WW11/oclcpuexp-2021.11.3.0.09_rel.tar.gz
+ocl_cpu_rt_ver=2021.11.3.0.09
+# https://github.com/intel/llvm/releases/download/2021-WW11/win-oclcpuexp-2021.11.3.0.09_rel.zip
+ocl_cpu_rt_ver_win=2021.11.3.0.09
 # Same GPU driver supports Level Zero and OpenCL
-# https://github.com/intel/compute-runtime/releases/tag/21.08.19096
-ocl_gpu_rt_ver=21.08.19096
+# https://github.com/intel/compute-runtime/releases/tag/21.09.19150
+ocl_gpu_rt_ver=21.09.19150
 # Same GPU driver supports Level Zero and OpenCL
 # https://downloadmirror.intel.com/30266/a08/igfx_win10_100.9316.zip
 ocl_gpu_rt_ver_win=27.20.100.9316
@@ -19,21 +19,21 @@ tbb_ver=2021.2.0.236
 # https://github.com/oneapi-src/oneTBB/releases/download/v2021.1.1/oneapi-tbb-2021.1.1-win.zip
 tbb_ver_win=2021.2.0.221
 
-# https://github.com/intel/llvm/releases/download/2021-WW10/fpgaemu-2021.11.3.0.02_rel.tar.gz
-ocl_fpga_emu_ver=2021.11.3.0.02
-# https://github.com/intel/llvm/releases/download/2021-WW10/win-fpgaemu-2021.11.3.0.02_rel.zip
-ocl_fpga_emu_ver_win=2021.11.3.0.02
-fpga_ver=20210205_000005
+# https://github.com/intel/llvm/releases/download/2021-WW11/fpgaemu-2021.11.3.0.09_rel.tar.gz
+ocl_fpga_emu_ver=2021.11.3.0.09
+# https://github.com/intel/llvm/releases/download/2021-WW11/win-fpgaemu-2021.11.3.0.09_rel.zip
+ocl_fpga_emu_ver_win=2021.11.3.0.09
+fpga_ver=20210205_000003
 fpga_ver_win=20210204_000003_signed_bom_fixed
 ocloc_ver_win=27.20.100.9168
 
 [DRIVER VERSIONS]
-cpu_driver_lin=2021.11.3.0.02
-cpu_driver_win=2021.11.3.0.02
-gpu_driver_lin=21.08.19096
+cpu_driver_lin=2021.11.3.0.09
+cpu_driver_win=2021.11.3.0.09
+gpu_driver_lin=21.09.19150
 gpu_driver_win=27.20.100.9316
-fpga_driver_lin=2021.11.3.0.02
-fpga_driver_win=2021.11.3.0.02
+fpga_driver_lin=2021.11.3.0.09
+fpga_driver_win=2021.11.3.0.09
 # NVidia CUDA driver
 # TODO provide URL for CUDA driver
 nvidia_gpu_driver_lin=435.21

clang/include/clang/Basic/Attr.td

@@ -2038,7 +2038,7 @@ def IntelFPGAMerge : Attr {
   let Documentation = [IntelFPGAMergeAttrDocs];
 }
 
-def IntelFPGAMaxReplicates : Attr {
+def IntelFPGAMaxReplicates : InheritableAttr {
   let Spellings = [CXX11<"intelfpga","max_replicates">,
                    CXX11<"intel","max_replicates">];
   let Args = [ExprArgument<"Value">];

clang/include/clang/Basic/CodeGenOptions.def

@@ -417,6 +417,9 @@ CODEGENOPT(PassByValueIsNoAlias, 1, 0)
 /// according to the field declaring type width.
 CODEGENOPT(AAPCSBitfieldWidth, 1, 1)
 
+// Whether to instrument SPIR device code with ITT annotations
+CODEGENOPT(SPIRITTAnnotations, 1, 0)
+
 #undef CODEGENOPT
 #undef ENUM_CODEGENOPT
 #undef VALUE_CODEGENOPT

clang/include/clang/Basic/DiagnosticSemaKinds.td

@@ -3195,6 +3195,9 @@ def warn_dllimport_dropped_from_inline_function : Warning<
   InGroup<IgnoredAttributes>;
 def warn_attribute_ignored : Warning<"%0 attribute ignored">,
   InGroup<IgnoredAttributes>;
+def warn_attribute_on_direct_kernel_callee_only : Warning<"%0 attribute allowed"
+  " only on a function directly called from a SYCL kernel function; attribute ignored">,
+  InGroup<IgnoredAttributes>;
 def warn_nothrow_attribute_ignored : Warning<"'nothrow' attribute conflicts with"
   " exception specification; attribute ignored">,
   InGroup<IgnoredAttributes>;

clang/include/clang/Basic/LangOptions.def

@@ -246,7 +246,6 @@ LANGOPT(GPUMaxThreadsPerBlock, 32, 1024, "default max threads per block for kern
 LANGOPT(GPUDeferDiag, 1, 0, "defer host/device related diagnostic messages for CUDA/HIP")
 LANGOPT(GPUExcludeWrongSideOverloads, 1, 0, "always exclude wrong side overloads in overloading resolution for CUDA/HIP")
 
-LANGOPT(SYCL              , 1, 0, "SYCL")
 LANGOPT(SYCLIsDevice      , 1, 0, "Generate code for SYCL device")
 LANGOPT(SYCLIsHost        , 1, 0, "SYCL host compilation")
 LANGOPT(SYCLAllowFuncPtr  , 1, 0, "Allow function pointers in SYCL device code")

clang/include/clang/Driver/Options.td

@@ -2418,6 +2418,10 @@ def fsycl_device_code_lower_esimd : Flag<["-"], "fsycl-device-code-lower-esimd">
   Flags<[CC1Option, CoreOption]>, HelpText<"Lower ESIMD-specific constructs">;
 def fno_sycl_device_code_lower_esimd : Flag<["-"], "fno-sycl-device-code-lower-esimd">,
   Flags<[CC1Option, CoreOption]>, HelpText<"Do not lower ESIMD-specific constructs">;
+def fsycl_instrument_device_code : Flag<["-"], "fsycl-instrument-device-code">,
+  Group<sycl_Group>, Flags<[CC1Option, CoreOption]>,
+  HelpText<"Add ITT instrumentation intrinsics calls">,
+  MarshallingInfoFlag<CodeGenOpts<"SPIRITTAnnotations">>;
 defm sycl_id_queries_fit_in_int: OptInFFlag<"sycl-id-queries-fit-in-int", "Assume", "Do not assume", " that SYCL ID queries fit within MAX_INT.", [CC1Option,CoreOption], LangOpts<"SYCLValueFitInMaxInt">>;
 def fsycl_use_bitcode : Flag<["-"], "fsycl-use-bitcode">,
   Flags<[CC1Option, CoreOption]>, HelpText<"Use LLVM bitcode instead of SPIR-V in fat objects">;
@@ -4287,19 +4291,14 @@ defm whole_file : BooleanFFlag<"whole-file">, Group<gfortran_Group>;
 def reuse_exe_EQ : Joined<["-"], "reuse-exe=">, Flags<[CoreOption]>,
   HelpText<"Speed up FPGA aoc compile if the device code in <exe> is unchanged.">,
   MetaVarName<"<exe>">;
-defm sycl : BoolOption<"f", "sycl",
-  LangOpts<"SYCL">, DefaultFalse,
-  PosFlag<SetTrue, [CC1Option], "Enable">, NegFlag<SetFalse, [], "Disable">,
-  BothFlags<[CoreOption], " SYCL kernels compilation for device">>,
-  Group<sycl_Group>;
-def sycl_std_EQ : Joined<["-"], "sycl-std=">, Group<sycl_Group>, Flags<[CC1Option, NoArgumentUnused, CoreOption]>,
-  HelpText<"SYCL language standard to compile for.">, Values<"2020,2017,121,1.2.1,sycl-1.2.1">,
-  NormalizedValues<["SYCL_2020", "SYCL_2017", "SYCL_2017", "SYCL_2017", "SYCL_2017"]>, NormalizedValuesScope<"LangOptions">,
-  MarshallingInfoString<LangOpts<"SYCLVersion">, "SYCL_None">, ShouldParseIf<fsycl.KeyPath>, AutoNormalizeEnum;
+def fsycl : Flag<["-"], "fsycl">, Flags<[NoXarchOption, CoreOption]>, Group<sycl_Group>,
+  HelpText<"Enables SYCL kernels compilation for device">;
+def fno_sycl : Flag<["-"], "fno-sycl">, Flags<[NoXarchOption, CoreOption]>, Group<sycl_Group>,
+  HelpText<"Disables SYCL kernels compilation for device">;
 defm sycl_esimd: BoolFOption<"sycl-explicit-simd",
   LangOpts<"SYCLExplicitSIMD">, DefaultFalse,
   PosFlag<SetTrue, [CC1Option], "Enable">, NegFlag<SetFalse, [], "Disable">,
-  BothFlags<[NoArgumentUnused, CoreOption], " SYCL explicit SIMD extension.">>;
+  BothFlags<[NoArgumentUnused, CoreOption], "SYCL explicit SIMD extension.">>;
 defm sycl_early_optimizations : OptOutFFlag<"sycl-early-optimizations", "Enable", "Disable", " standard optimization pipeline for SYCL device compiler", [CoreOption]>;
 def fsycl_dead_args_optimization : Flag<["-"], "fsycl-dead-args-optimization">,
   Group<sycl_Group>, Flags<[NoArgumentUnused, CoreOption]>, HelpText<"Enables "
@@ -5513,8 +5512,7 @@ def fopenmp_host_ir_file_path : Separate<["-"], "fopenmp-host-ir-file-path">,
 
 def fsycl_is_device : Flag<["-"], "fsycl-is-device">,
   HelpText<"Generate code for SYCL device.">,
-  MarshallingInfoFlag<LangOpts<"SYCLIsDevice">>,
-  ShouldParseIf<fsycl.KeyPath>;
+  MarshallingInfoFlag<LangOpts<"SYCLIsDevice">>;
 def fsycl_is_host : Flag<["-"], "fsycl-is-host">,
   HelpText<"SYCL host compilation">,
   MarshallingInfoFlag<LangOpts<"SYCLIsHost">>;
@@ -5533,6 +5531,16 @@ def fenable_sycl_dae : Flag<["-"], "fenable-sycl-dae">,
 
 } // let Flags = [CC1Option, NoDriverOption]
 
+def sycl_std_EQ : Joined<["-"], "sycl-std=">, Group<sycl_Group>,
+  Flags<[CC1Option, NoArgumentUnused, CoreOption]>,
+  HelpText<"SYCL language standard to compile for.">,
+  Values<"2020,2017,121,1.2.1,sycl-1.2.1">,
+  NormalizedValues<["SYCL_2020", "SYCL_2017", "SYCL_2017", "SYCL_2017", "SYCL_2017"]>,
+  NormalizedValuesScope<"LangOptions">,
+  MarshallingInfoString<LangOpts<"SYCLVersion">, "SYCL_None">,
+  AutoNormalizeEnum,
+  ShouldParseIf<!strconcat(fsycl_is_device.KeyPath, "||", fsycl_is_host.KeyPath)>;
+
 defm cuda_approx_transcendentals : BoolFOption<"cuda-approx-transcendentals",
   LangOpts<"CUDADeviceApproxTranscendentals">, DefaultFalse,
   PosFlag<SetTrue, [CC1Option], "Use">, NegFlag<SetFalse, [], "Don't use">,

clang/include/clang/Sema/Sema.h

@@ -10234,6 +10234,12 @@ class Sema final {
                                 Expr *E);
   SYCLIntelLoopFuseAttr *
   MergeSYCLIntelLoopFuseAttr(Decl *D, const SYCLIntelLoopFuseAttr &A);
+  void AddIntelFPGAPrivateCopiesAttr(Decl *D, const AttributeCommonInfo &CI,
+                                     Expr *E);
+  void AddIntelFPGAMaxReplicatesAttr(Decl *D, const AttributeCommonInfo &CI,
+                                     Expr *E);
+  IntelFPGAMaxReplicatesAttr *
+  MergeIntelFPGAMaxReplicatesAttr(Decl *D, const IntelFPGAMaxReplicatesAttr &A);
 
   /// AddAlignedAttr - Adds an aligned attribute to a particular declaration.
   void AddAlignedAttr(Decl *D, const AttributeCommonInfo &CI, Expr *E,
@@ -13017,6 +13023,7 @@ class Sema final {
 
   bool isKnownGoodSYCLDecl(const Decl *D);
   void checkSYCLDeviceVarDecl(VarDecl *Var);
+  void copySYCLKernelAttrs(const CXXRecordDecl *KernelObj);
   void ConstructOpenCLKernel(FunctionDecl *KernelCallerFunc, MangleContext &MC);
   void MarkDevice();
 
@@ -13093,13 +13100,6 @@ void Sema::addIntelSingleArgAttr(Decl *D, const AttributeCommonInfo &CI,
       return;
     E = ICE.get();
     int32_t ArgInt = ArgVal.getSExtValue();
-    if (CI.getParsedKind() == ParsedAttr::AT_IntelFPGAMaxReplicates) {
-      if (ArgInt <= 0) {
-        Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
-            << CI << /*positive*/ 0;
-        return;
-      }
-    }
     if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim) {
       if (ArgInt < 0) {
         Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
@@ -13114,19 +13114,6 @@ void Sema::addIntelSingleArgAttr(Decl *D, const AttributeCommonInfo &CI,
         return;
       }
     }
-    if (CI.getParsedKind() == ParsedAttr::AT_IntelFPGAPrivateCopies) {
-      if (ArgInt < 0) {
-        Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
-            << CI << /*non-negative*/ 1;
-        return;
-      }
-    }
-  }
-
-  if (CI.getParsedKind() == ParsedAttr::AT_IntelFPGAPrivateCopies) {
-    if (!D->hasAttr<IntelFPGAMemoryAttr>())
-      D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
-          Context, IntelFPGAMemoryAttr::Default));
   }
 
   D->addAttr(::new (Context) AttrType(Context, CI, E));

clang/lib/AST/ASTContext.cpp

@@ -2098,7 +2098,7 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T) const {
       Align = Target->getDoubleAlign();
       break;
     case BuiltinType::LongDouble:
-      if (((getLangOpts().SYCL && getLangOpts().SYCLIsDevice) ||
+      if ((getLangOpts().SYCLIsDevice ||
            (getLangOpts().OpenMP && getLangOpts().OpenMPIsDevice)) &&
           AuxTarget != nullptr &&
           (Target->getLongDoubleWidth() != AuxTarget->getLongDoubleWidth() ||

clang/lib/CodeGen/BackendUtil.cpp

@@ -72,6 +72,7 @@
 #include "llvm/Transforms/Instrumentation/InstrProfiling.h"
 #include "llvm/Transforms/Instrumentation/MemProfiler.h"
 #include "llvm/Transforms/Instrumentation/MemorySanitizer.h"
+#include "llvm/Transforms/Instrumentation/SPIRITTAnnotations.h"
 #include "llvm/Transforms/Instrumentation/SanitizerCoverage.h"
 #include "llvm/Transforms/Instrumentation/ThreadSanitizer.h"
 #include "llvm/Transforms/ObjCARC.h"
@@ -948,6 +949,16 @@ void EmitAssemblyHelper::EmitAssembly(BackendAction Action,
       LangOpts.EnableDAEInSpirKernels)
     PerModulePasses.add(createDeadArgEliminationSYCLPass());
 
+  // Add SPIRITTAnnotations pass to the pass manager if
+  // -fsycl-instrument-device-code option was passed. This option can be
+  // used only with spir triple.
+  if (CodeGenOpts.SPIRITTAnnotations) {
+    if (!llvm::Triple(TheModule->getTargetTriple()).isSPIR())
+      llvm::report_fatal_error(
+          "ITT annotations can only by added to a module with spir target");
+    PerModulePasses.add(createSPIRITTAnnotationsPass());
+  }
+
   switch (Action) {
   case Backend_EmitNothing:
     break;

clang/lib/CodeGen/TargetInfo.cpp

@@ -9999,7 +9999,7 @@ LangAS SPIRTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
   LangAS AddrSpace = D->getType().getAddressSpace();
   assert(AddrSpace == LangAS::Default || isTargetAddressSpace(AddrSpace) ||
          // allow applying clang AST address spaces in SYCL mode
-         (CGM.getLangOpts().SYCL && CGM.getLangOpts().SYCLIsDevice));
+         CGM.getLangOpts().SYCLIsDevice);
   if (AddrSpace != LangAS::Default)
     return AddrSpace;